camera: rockchip: camsys_drv: 0.0x21.0xe

1) correct mipiphy_hsfreqrange of 3368.
2) add csi-phy timing setting for 3368.

Change-Id: Ia5203dcd8f01bc8989d5bb41a1b2af71bb91f607
Signed-off-by: dalong.zhang <dalon.zhang@rock-chips.com>

diff --git a/drivers/media/video/rk_camsys/camsys_internal.h b/drivers/media/video/rk_camsys/camsys_internal.h
index 17068f639fc64461a4430b969383b05612c4e3fd..2c1109bbc07516de87362685ea142c9e1a25fbc3 100644 (file)
--- a/drivers/media/video/rk_camsys/camsys_internal.h
+++ b/drivers/media/video/rk_camsys/camsys_internal.h
@@ -159,8 +159,11 @@
        1) support rk3288.
 *v0.0x21.0xd:
        1) modify mipiphy_hsfreqrange for 3368.
+*v0.0x21.0xe
+       1) correct mipiphy_hsfreqrange of 3368.
+       2) add csi-phy timing setting for 3368.
 */
-#define CAMSYS_DRIVER_VERSION                   KERNEL_VERSION(0, 0x21, 0xd)
+#define CAMSYS_DRIVER_VERSION                   KERNEL_VERSION(0, 0x21, 0xe)
 
 #define CAMSYS_PLATFORM_DRV_NAME                "RockChip-CamSys"
 #define CAMSYS_PLATFORM_MARVIN_NAME             "Platform_MarvinDev"

diff --git a/drivers/media/video/rk_camsys/camsys_soc_rk3366.c b/drivers/media/video/rk_camsys/camsys_soc_rk3366.c
index 60c9c062ef3ce12bcb3d0025a037c6902b0ec5b3..a4a1bec59c37b6cf5583a933ea9a5f11aaabba2a 100644 (file)
--- a/drivers/media/video/rk_camsys/camsys_soc_rk3366.c
+++ b/drivers/media/video/rk_camsys/camsys_soc_rk3366.c
@@ -19,11 +19,11 @@ static struct mipiphy_hsfreqrange_s mipiphy_hsfreqrange[] = {
        {500, 600, 0x07},
        {600, 700, 0x08},
        {700, 800, 0x09},
-       {800, 1000, 0x10},
-       {1000, 1200, 0x11},
-       {1200, 1400, 0x12},
-       {1400, 1600, 0x13},
-       {1600, 1800, 0x14}
+       {800, 1000, 0xa},
+       {1000, 1100, 0xb},
+       {1100, 1250, 0xc},
+       {1250, 1350, 0xd},
+       {1350, 1500, 0xe}
 };
 
 #if 0
@@ -127,6 +127,22 @@ camsys_mipiphy_soc_para_t *para)
                        | (1 << ISP_MIPI_CSI_HOST_SEL_OFFSET_BIT));
                */
                /* phy start */
+               write_csiphy_reg(MIPI_CSI_DPHY_CTRL_PWRCTL_OFFSET, 0xe4);
+
+               /* set data lane num and enable clock lane */
+               write_csiphy_reg(MIPI_CSI_DPHY_LANEX_THS_SETTLE_OFFSET,
+                       ((para->phy->data_en_bit << 2) | (0x1 << 6) | 0x1));
+               /* Reset dphy analog part */
+               write_csiphy_reg(MIPI_CSI_DPHY_CTRL_PWRCTL_OFFSET, 0xe0);
+               usleep_range(500, 1000);
+               /* Reset dphy digital part */
+               write_csiphy_reg(MIPI_CSI_DPHY_CTRL_DIG_RST_OFFSET, 0x1e);
+               write_csiphy_reg(MIPI_CSI_DPHY_CTRL_DIG_RST_OFFSET, 0x1f);
+
+               write_grf_reg(GRF_SOC_CON6_OFFSET,
+                       MIPI_CSI_DPHY_RX_FORCERXMODE_MASK |
+                       MIPI_CSI_DPHY_RX_FORCERXMODE_BIT);
+
                write_csiphy_reg
                        ((MIPI_CSI_DPHY_LANEX_THS_SETTLE_OFFSET + 0x100),
                        hsfreqrange |
@@ -155,11 +171,10 @@ camsys_mipiphy_soc_para_t *para)
                        (read_csiphy_reg(MIPI_CSI_DPHY_LANEX_THS_SETTLE_OFFSET
                                + 0x300) & (~0xf)));
                }
-
-               /*set data lane num and enable clock lane */
-               write_csiphy_reg(0x00, ((para->phy->data_en_bit << 2)
-                       | (0x1 << 6) | 0x1));
-
+               /*
+                * MIPI CTRL bit8:11 SHUTDOWN_LANE are invert
+                * connect to dphy pin_enable_x
+                */
                base =
                        (unsigned long)
                        para->camsys_dev->devmems.registermem->vir_base;
@@ -225,7 +240,7 @@ camsys_dev_t *camsys_dev, camsys_soc_cfg_t cfg_cmd, void *cfg_para)
                else
                        __raw_writel(0x00, (void *)(camsys_dev->rk_isp_base +
                                MRV_AFM_BASE + VI_IRCL));
-                       camsys_trace(1, "Isp self soft rst: %ld", reset);
+                       camsys_trace(2, "Isp self soft rst: %ld", reset);
                break;
        }
 

diff --git a/drivers/media/video/rk_camsys/camsys_soc_rk3366.h b/drivers/media/video/rk_camsys/camsys_soc_rk3366.h
index 3128d0f7396a8d55548fda436e12a73115499e11..a0e9ae2c37f4741b8cf32220d4b29aca1c6a6890 100644 (file)
--- a/drivers/media/video/rk_camsys/camsys_soc_rk3366.h
+++ b/drivers/media/video/rk_camsys/camsys_soc_rk3366.h
@@ -89,6 +89,9 @@
 */
 #define MIPI_CSI_DPHY_LANEX_MSB_EN_OFFSET  (0x38)
 
+#define MIPI_CSI_DPHY_RX_FORCERXMODE_MASK (0x0f << 24)
+#define MIPI_CSI_DPHY_RX_FORCERXMODE_BIT (0 << 8)
+
 #define CSIHOST_N_LANES_OFFSET 0x04
 #define CSIHOST_N_LANES_OFFSET_BIT (0)
 

diff --git a/drivers/media/video/rk_camsys/camsys_soc_rk3368.c b/drivers/media/video/rk_camsys/camsys_soc_rk3368.c
index 2afac1e90386a1dbedc66962cd7e5d7c0a78e119..32a7dafd11d787c1faba33ed911a953a11d8215f 100644 (file)
--- a/drivers/media/video/rk_camsys/camsys_soc_rk3368.c
+++ b/drivers/media/video/rk_camsys/camsys_soc_rk3368.c
@@ -20,11 +20,11 @@ static struct mipiphy_hsfreqrange_s mipiphy_hsfreqrange[] = {
        {500, 600, 0x07},
        {600, 700, 0x08},
        {700, 800, 0x09},
-       {800, 1000, 0x10},
-       {1000, 1200, 0x11},
-       {1200, 1400, 0x12},
-       {1400, 1600, 0x13},
-       {1600, 1800, 0x14}
+       {800, 1000, 0xa},
+       {1000, 1100, 0xb},
+       {1100, 1250, 0xc},
+       {1250, 1350, 0xd},
+       {1350, 1500, 0xe}
 };
 
 #if 0
@@ -124,7 +124,23 @@ static int camsys_rk3368_mipihpy_cfg(camsys_mipiphy_soc_para_t *para)
        write_grf_reg(GRF_SOC_CON6_OFFSET, ISP_MIPI_CSI_HOST_SEL_OFFSET_MASK
                                | (1 << ISP_MIPI_CSI_HOST_SEL_OFFSET_BIT));
 
-       /* phy start */
+               /* phy start */
+               write_csiphy_reg(MIPI_CSI_DPHY_CTRL_PWRCTL_OFFSET, 0xe4);
+
+               /* set data lane num and enable clock lane */
+               write_csiphy_reg(MIPI_CSI_DPHY_LANEX_THS_SETTLE_OFFSET,
+                       ((para->phy->data_en_bit << 2) | (0x1 << 6) | 0x1));
+               /* Reset dphy analog part */
+               write_csiphy_reg(MIPI_CSI_DPHY_CTRL_PWRCTL_OFFSET, 0xe0);
+               usleep_range(500, 1000);
+               /* Reset dphy digital part */
+               write_csiphy_reg(MIPI_CSI_DPHY_CTRL_DIG_RST_OFFSET, 0x1e);
+               write_csiphy_reg(MIPI_CSI_DPHY_CTRL_DIG_RST_OFFSET, 0x1f);
+
+               write_grf_reg(GRF_SOC_CON6_OFFSET,
+                       MIPI_CSI_DPHY_RX_FORCERXMODE_MASK |
+                       MIPI_CSI_DPHY_RX_FORCERXMODE_BIT);
+
        write_csiphy_reg((MIPI_CSI_DPHY_LANEX_THS_SETTLE_OFFSET + 0x100),
                hsfreqrange |
                (read_csiphy_reg(MIPI_CSI_DPHY_LANEX_THS_SETTLE_OFFSET
@@ -152,11 +168,10 @@ static int camsys_rk3368_mipihpy_cfg(camsys_mipiphy_soc_para_t *para)
                        (read_csiphy_reg(MIPI_CSI_DPHY_LANEX_THS_SETTLE_OFFSET
                        + 0x300) & (~0xf)));
        }
-
-       /*set data lane num and enable clock lane */
-       write_csiphy_reg(0x00, ((para->phy->data_en_bit << 2)
-                                       | (0x1 << 6) | 0x1));
-
+               /*
+                * MIPI CTRL bit8:11 SHUTDOWN_LANE are invert
+                * connect to dphy pin_enable_x
+                */
        base = (unsigned long)para->camsys_dev->devmems.registermem->vir_base;
        *((unsigned int *)(base + (MRV_MIPI_BASE + MRV_MIPI_CTRL)))
                                                        &= ~(0x0f << 8);

diff --git a/drivers/media/video/rk_camsys/camsys_soc_rk3368.h b/drivers/media/video/rk_camsys/camsys_soc_rk3368.h
index 12ec006284e32e2f490c93d20ea9fc6718e3933a..b9862ed6574d01fc2b488c3bab650c1b75b61afa 100644 (file)
--- a/drivers/media/video/rk_camsys/camsys_soc_rk3368.h
+++ b/drivers/media/video/rk_camsys/camsys_soc_rk3368.h
@@ -89,6 +89,9 @@
 */
 #define MIPI_CSI_DPHY_LANEX_MSB_EN_OFFSET  (0x38)
 
+#define MIPI_CSI_DPHY_RX_FORCERXMODE_MASK (0x0f << 24)
+#define MIPI_CSI_DPHY_RX_FORCERXMODE_BIT (0 << 8)
+
 #define CSIHOST_N_LANES_OFFSET 0x04
 #define CSIHOST_N_LANES_OFFSET_BIT (0)