Use target specific interface instead of forcing it to be target-generic

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@7413 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/lib/Target/X86/InstSelectSimple.cpp b/lib/Target/X86/InstSelectSimple.cpp
index 83987df7e29b316e0468df844e398921f5a99469..79dbedcdc1111f7624fa51382c76bb79358de75d 100644 (file)
--- a/lib/Target/X86/InstSelectSimple.cpp
+++ b/lib/Target/X86/InstSelectSimple.cpp
@@ -219,9 +219,12 @@ namespace {
     /// of the long value.
     ///
     unsigned makeAnotherReg(const Type *Ty) {
+      assert(dynamic_cast<const X86RegisterInfo*>(TM.getRegisterInfo()) &&
+             "Current target doesn't have X86 reg info??");
+      const X86RegisterInfo *MRI =
+        static_cast<const X86RegisterInfo*>(TM.getRegisterInfo());
       if (Ty == Type::LongTy || Ty == Type::ULongTy) {
-       const TargetRegisterClass *RC =
-         TM.getRegisterInfo()->getRegClassForType(Type::IntTy);
+       const TargetRegisterClass *RC = MRI->getRegClassForType(Type::IntTy);
        // Create the lower part
        F->getSSARegMap()->createVirtualRegister(RC);
        // Create the upper part.
@@ -229,8 +232,7 @@ namespace {
       }
 
       // Add the mapping of regnumber => reg class to MachineFunction
-      const TargetRegisterClass *RC =
-       TM.getRegisterInfo()->getRegClassForType(Ty);
+      const TargetRegisterClass *RC = MRI->getRegClassForType(Ty);
       return F->getSSARegMap()->createVirtualRegister(RC);
     }
 

diff --git a/lib/Target/X86/X86ISelSimple.cpp b/lib/Target/X86/X86ISelSimple.cpp
index 83987df7e29b316e0468df844e398921f5a99469..79dbedcdc1111f7624fa51382c76bb79358de75d 100644 (file)
--- a/lib/Target/X86/X86ISelSimple.cpp
+++ b/lib/Target/X86/X86ISelSimple.cpp
@@ -219,9 +219,12 @@ namespace {
     /// of the long value.
     ///
     unsigned makeAnotherReg(const Type *Ty) {
+      assert(dynamic_cast<const X86RegisterInfo*>(TM.getRegisterInfo()) &&
+             "Current target doesn't have X86 reg info??");
+      const X86RegisterInfo *MRI =
+        static_cast<const X86RegisterInfo*>(TM.getRegisterInfo());
       if (Ty == Type::LongTy || Ty == Type::ULongTy) {
-       const TargetRegisterClass *RC =
-         TM.getRegisterInfo()->getRegClassForType(Type::IntTy);
+       const TargetRegisterClass *RC = MRI->getRegClassForType(Type::IntTy);
        // Create the lower part
        F->getSSARegMap()->createVirtualRegister(RC);
        // Create the upper part.
@@ -229,8 +232,7 @@ namespace {
       }
 
       // Add the mapping of regnumber => reg class to MachineFunction
-      const TargetRegisterClass *RC =
-       TM.getRegisterInfo()->getRegClassForType(Ty);
+      const TargetRegisterClass *RC = MRI->getRegClassForType(Ty);
       return F->getSSARegMap()->createVirtualRegister(RC);
     }