rk3188: uboot display support; use support_uboot_display to get status

diff --git a/arch/arm/mach-rk3188/clock_data.c b/arch/arm/mach-rk3188/clock_data.c
index ac126ad98aa49a35282bb96d08d02d3557743aa6..e5d81416d11a1c601d1a0969a9c3abb4ecb4f34d 100755 (executable)
--- a/arch/arm/mach-rk3188/clock_data.c
+++ b/arch/arm/mach-rk3188/clock_data.c
@@ -36,7 +36,7 @@
 #define CLK_LOOPS_RATE_REF (1200UL) //Mhz
 #define CLK_LOOPS_RECALC(new_rate)  div_u64(CLK_LOOPS_JIFFY_REF*(new_rate),CLK_LOOPS_RATE_REF*MHZ)
 void rk30_clk_dump_regs(void);
-
+static int flag_uboot_display = 0;
 //flags bit
 //has extern 27mhz
 #define CLK_FLG_EXT_27MHZ                      (1<<0)
@@ -3034,6 +3034,16 @@ static void __init rk30_init_enable_clocks(void)
        clk_enable_nolock(&atclk_cpu);
        //clk_enable_nolock(&hclk_cpu);
        clk_enable_nolock(&ahb2apb_cpu);
+       if (flag_uboot_display) {
+               clk_enable_nolock(&dclk_lcdc0);
+               clk_enable_nolock(&dclk_lcdc1);
+               clk_enable_nolock(&clk_hclk_lcdc0);
+               clk_enable_nolock(&clk_hclk_lcdc1);
+               clk_enable_nolock(&clk_aclk_lcdc0);
+               clk_enable_nolock(&clk_aclk_lcdc1);
+               clk_enable_nolock(&aclk_lcdc0_pre);
+               clk_enable_nolock(&aclk_lcdc1_pre);
+       }
        #if 0
         clk_enable_nolock(&clk_gpu);
         clk_enable_nolock(&aclk_gpu);
@@ -3045,17 +3055,12 @@ static void __init rk30_init_enable_clocks(void)
         clk_enable_nolock(&aclk_vdpu);
         clk_enable_nolock(&hclk_vdpu);
 
-        clk_enable_nolock(&aclk_lcdc0_pre);
-        clk_enable_nolock(&aclk_lcdc1_pre);
 
         clk_enable_nolock(&aclk_periph);
        clk_enable_nolock(&pclk_periph);
        clk_enable_nolock(&hclk_periph);
        #endif
        #if 0
-        clk_enable_nolock(&dclk_lcdc0);
-        clk_enable_nolock(&dclk_lcdc1);
-       
         clk_enable_nolock(&cif_out_pll);
         clk_enable_nolock(&cif0_out_div);
 
@@ -3171,8 +3176,6 @@ static void __init rk30_init_enable_clocks(void)
        clk_enable_nolock(&clk_hclk_ahb2apb);
        clk_enable_nolock(&clk_hclk_vio_bus);
        #if 0
-       clk_enable_nolock(&clk_hclk_lcdc0);
-       clk_enable_nolock(&clk_hclk_lcdc1);
        clk_enable_nolock(&clk_hclk_cif0);
        clk_enable_nolock(&clk_hclk_ipp);
        clk_enable_nolock(&clk_hclk_rga);
@@ -3248,14 +3251,12 @@ static void __init rk30_init_enable_clocks(void)
        /*************************aclk_lcdc0***********************/
 #if 1
        //clk_enable_nolock(&clk_aclk_vio0);
-       //clk_enable_nolock(&clk_aclk_lcdc0);
        //clk_enable_nolock(&clk_aclk_cif0);
        //clk_enable_nolock(&clk_aclk_ipp);
 #endif
        /*************************aclk_lcdc1***********************/
 #if 1
        //clk_enable_nolock(&clk_aclk_vio1);
-       //clk_enable_nolock(&clk_aclk_lcdc1);
        //clk_enable_nolock(&clk_aclk_rga);
 #endif
        /************************power domain**********************/
@@ -3473,11 +3474,13 @@ static void div_clk_for_pll_init(void)
        clock_set_max_div(&aclk_vdpu);
        clock_set_max_div(&aclk_vepu);
        clock_set_max_div(&aclk_gpu);
-       clock_set_max_div(&aclk_lcdc0_pre);
-       clock_set_max_div(&aclk_lcdc1_pre);
+       if (!flag_uboot_display) {
+               clock_set_max_div(&aclk_lcdc0_pre);
+               clock_set_max_div(&aclk_lcdc1_pre);
+               clock_set_max_div(&dclk_lcdc0);
+               clock_set_max_div(&dclk_lcdc1);
+       }
        clock_set_max_div(&aclk_periph);
-       clock_set_max_div(&dclk_lcdc0);
-       clock_set_max_div(&dclk_lcdc1);
        clock_set_max_div(&cif0_out_div);
        clock_set_max_div(&clk_i2s0_div);
        clock_set_max_div(&clk_spdif_div);
@@ -3495,11 +3498,13 @@ static u8 pll_flag = 0;
 static void __init rk30_clock_common_init(unsigned long gpll_rate, unsigned long cpll_rate)
 {
        //general
-       clk_set_rate_nolock(&general_pll_clk, gpll_rate);
+       if (!flag_uboot_display)
+               clk_set_rate_nolock(&general_pll_clk, gpll_rate);
        lpj_gpll = CLK_LOOPS_RECALC(general_pll_clk.rate);
 
        //code pll
-       clk_set_rate_nolock(&codec_pll_clk, cpll_rate);
+       if (!flag_uboot_display)
+               clk_set_rate_nolock(&codec_pll_clk, cpll_rate);
 
        cpu_axi_init();
        clk_set_rate_nolock(&clk_core, 816 * MHZ);
@@ -3532,19 +3537,20 @@ static void __init rk30_clock_common_init(unsigned long gpll_rate, unsigned long
        //auto pll sel
        //clk_set_parent_nolock(&clk_hsadc_pll_div, &general_pll_clk);
 
-       //lcdc0 lcd auto sel pll
-       clk_set_parent_nolock(&dclk_lcdc0, &general_pll_clk);
-       clk_set_parent_nolock(&dclk_lcdc1, &general_pll_clk);
+       if (!flag_uboot_display) {
+               //lcdc0 lcd auto sel pll
+               clk_set_parent_nolock(&dclk_lcdc0, &general_pll_clk);
+               clk_set_parent_nolock(&dclk_lcdc1, &general_pll_clk);
 
+               //axi lcdc auto sel
+               clk_set_parent_nolock(&aclk_lcdc0_pre, &general_pll_clk);
+               clk_set_parent_nolock(&aclk_lcdc1_pre, &general_pll_clk);
+               clk_set_rate_nolock(&aclk_lcdc0_pre, 300 * MHZ);
+               clk_set_rate_nolock(&aclk_lcdc1_pre, 300 * MHZ);
+       }
        //cif
        clk_set_parent_nolock(&cif_out_pll, &general_pll_clk);
 
-       //axi lcdc auto sel
-       clk_set_parent_nolock(&aclk_lcdc0_pre, &general_pll_clk);
-       clk_set_parent_nolock(&aclk_lcdc1_pre, &general_pll_clk);
-       clk_set_rate_nolock(&aclk_lcdc0_pre, 300 * MHZ);
-       clk_set_rate_nolock(&aclk_lcdc1_pre, 300 * MHZ);
-
        //axi vepu auto sel
        //clk_set_parent_nolock(&aclk_vepu, &general_pll_clk);
        //clk_set_parent_nolock(&aclk_vdpu, &general_pll_clk);
@@ -3634,6 +3640,7 @@ void __init _rk30_clock_data_init(unsigned long gpll, unsigned long cpll, int fl
        rk30_clock_common_init(gpll, cpll);
        preset_lpj = loops_per_jiffy;
 
+
        //gpio6_b7
        //regfile_writel(0xc0004000,0x10c);
        //cru_writel(0x07000000,CRU_MISC_CON);
@@ -3648,7 +3655,21 @@ void __init rk30_clock_data_init(unsigned long gpll, unsigned long cpll, u32 fla
        _rk30_clock_data_init(gpll, cpll, flags);
        rk3188_dvfs_init();
 }
+#define STR_UBOOT_DISPLAY      "fastboot"
+static int __init bootloader_setup(char *str)
+{
+       if (0 == strncmp(str, STR_UBOOT_DISPLAY, strlen(STR_UBOOT_DISPLAY))) {
+               printk("CLKDATA_MSG: get uboot display\n");
+               flag_uboot_display = 1;
+       }
+       return 0;
+}
+early_param("androidboot.bootloader", bootloader_setup);
 
+int support_uboot_display(void)
+{
+       return flag_uboot_display;
+}
 /*
  * You can override arm_clk rate with armclk= cmdline option.
  */