implemented, llvm-mc --show-inst now uses it to print the
instruction opcode as well as the number.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@95929
91177308-0d34-0410-b5e6-
96231b3b80d8
class MCInst;
class raw_ostream;
class MCAsmInfo;
+class StringRef;
-
/// MCInstPrinter - This is an instance of a target assembly language printer
/// that converts an MCInst to valid target assembly syntax.
class MCInstPrinter {
/// printInst - Print the specified MCInst to the current raw_ostream.
///
virtual void printInst(const MCInst *MI) = 0;
+
+ /// getOpcodeName - Return the name of the specified opcode enum (e.g.
+ /// "MOV32ri") or empty if we can't resolve it.
+ virtual StringRef getOpcodeName(unsigned Opcode) const;
};
} // namespace llvm
raw_ostream &OS = GetCommentOS();
OS << "<MCInst #" << Inst.getOpcode();
+ StringRef InstName;
+ if (InstPrinter)
+ InstName = InstPrinter->getOpcodeName(Inst.getOpcode());
+ if (!InstName.empty())
+ OS << ' ' << InstName;
+
for (unsigned i = 0, e = Inst.getNumOperands(); i != e; ++i) {
OS << "\n ";
Inst.getOperand(i).print(OS, &MAI);
//===----------------------------------------------------------------------===//
#include "llvm/MC/MCInstPrinter.h"
+#include "llvm/ADT/StringRef.h"
using namespace llvm;
MCInstPrinter::~MCInstPrinter() {
}
+
+/// getOpcodeName - Return the name of the specified opcode enum (e.g.
+/// "MOV32ri") or empty if we can't resolve it.
+StringRef MCInstPrinter::getOpcodeName(unsigned Opcode) const {
+ return "";
+}
/// size, and 3) use of X86-64 extended registers.
static unsigned DetermineREXPrefix(const MCInst &MI, unsigned TSFlags,
const TargetInstrDesc &Desc) {
- unsigned REX = 0;
+ // Pseudo instructions shouldn't get here.
+ assert((TSFlags & X86II::FormMask) != X86II::Pseudo &&
+ "Can't encode pseudo instrs");
- // Pseudo instructions do not need REX prefix byte.
- if ((TSFlags & X86II::FormMask) == X86II::Pseudo)
- return 0;
+ unsigned REX = 0;
if (TSFlags & X86II::REX_W)
REX |= 1 << 3;