#define GPIO6_PB3_DO_HIGH 0x08000800
#define GPIO6_PB3_EN_MASK 0x08000800
#define GPIO6_PB3_UNEN_MASK 0x08000000
+#define GPIO6_PB1_DIR_OUT 0x02000200
+#define GPIO6_PB1_DO_LOW 0x02000000
+#define GPIO6_PB1_DO_HIGH 0x02000200
+#define GPIO6_PB1_EN_MASK 0x02000200
+#define GPIO6_PB1_UNEN_MASK 0x02000000
#define TWL60xx_IRQ_BASE (NR_GIC_IRQS + NR_GPIO_IRQS )
#ifdef CONFIG_TWL4030_CORE
}
#define PMU_POWER_SLEEP RK30_PIN6_PB3
-
+#define PMU_CHRG_DET_N RK30_PIN0_PC7
int tps80032_pre_init(void){
printk("%s\n", __func__);
gpio_request(PMU_POWER_SLEEP, "NULL");
gpio_direction_output(PMU_POWER_SLEEP, GPIO_LOW);
+
+ gpio_request(PMU_CHRG_DET_N, "NULL");
+ gpio_direction_output(PMU_CHRG_DET_N, GPIO_HIGH);
- twl_reg_write(PREQ1_RES_ASS_A,TWL_MODULE_PM_SLAVE_RES,0x0b);
- twl_reg_write(PREQ1_RES_ASS_B,TWL_MODULE_PM_SLAVE_RES,0x10);
+ twl_reg_write(PREQ1_RES_ASS_A,TWL_MODULE_PM_SLAVE_RES,0x2b);
+ twl_reg_write(PREQ1_RES_ASS_B,TWL_MODULE_PM_SLAVE_RES,0x50);
twl_reg_write(PREQ1_RES_ASS_C,TWL_MODULE_PM_SLAVE_RES,0x27);
twl_reg_write(PHOENIX_MSK_TRANSITION,TWL_MODULE_PM_MASTER,0x00);
twl_reg_write(PHOENIX_SENS_TRANSITION,TWL_MODULE_PM_MASTER,0xc0); //set pmu enter sleep on a preq1 rising edge
twl_reg_write(CLK32KG_CFG_STATE,TWL_MODULE_PM_SLAVE_RES,0x01); //set clk32kg on when we use
twl_reg_write(CLK32KAUDIO_CFG_STATE,TWL_MODULE_PM_SLAVE_RES,0x01); //set clk32kaudio on when we use
-// twl_reg_write(LDO5_CFG_TRANS,TWL_MODULE_PM_RECEIVER,0x03); //set ldo5 is disabled when in sleep mode
-// twl_reg_write(LDO7_CFG_TRANS,TWL_MODULE_PM_RECEIVER,0x03); //set ldo7 is disabled when in sleep mode
-
+ twl_reg_write(LDO5_CFG_TRANS,TWL_MODULE_PM_RECEIVER,0x03); //set ldo5 is disabled when in sleep mode
+ twl_reg_write(LDO7_CFG_TRANS,TWL_MODULE_PM_RECEIVER,0x03); //set ldo7 is disabled when in sleep mode
+ twl_reg_write(LDOUSB_CFG_TRANS,TWL_MODULE_PM_RECEIVER,0x03);
return 0;
}
void __sramfunc board_pmu_suspend(void)
{
+ #ifdef CONFIG_CLK_SWITCH_TO_32K //switch clk to 32k
+ grf_writel(GPIO6_PB1_DIR_OUT, GRF_GPIO6L_DIR_ADDR);
+ grf_writel(GPIO6_PB1_DO_HIGH, GRF_GPIO6L_DO_ADDR); //set gpio6_b1 output low
+ grf_writel(GPIO6_PB1_EN_MASK, GRF_GPIO6L_EN_ADDR);
+ #endif
+
grf_writel(GPIO6_PB3_DIR_OUT, GRF_GPIO6L_DIR_ADDR);
grf_writel(GPIO6_PB3_DO_HIGH, GRF_GPIO6L_DO_ADDR); //set gpio6_b3 output low
grf_writel(GPIO6_PB3_EN_MASK, GRF_GPIO6L_EN_ADDR);
+
}
void __sramfunc board_pmu_resume(void)
{
grf_writel(GPIO6_PB3_DIR_OUT, GRF_GPIO6L_DIR_ADDR);
grf_writel(GPIO6_PB3_DO_LOW, GRF_GPIO6L_DO_ADDR); //set gpio6_b3 output high
grf_writel(GPIO6_PB3_EN_MASK, GRF_GPIO6L_EN_ADDR);
+
+ #ifdef CONFIG_CLK_SWITCH_TO_32K //switch clk to 24M
+ grf_writel(GPIO6_PB1_DIR_OUT, GRF_GPIO6L_DIR_ADDR);
+ grf_writel(GPIO6_PB1_DO_LOW, GRF_GPIO6L_DO_ADDR); //set gpio6_b1 output low
+ grf_writel(GPIO6_PB1_EN_MASK, GRF_GPIO6L_EN_ADDR);
+ sram_32k_udelay(10000);
+ #else
sram_udelay(2000);
+ #endif
}
static struct twl4030_platform_data tps80032_data = {