net: phy: dp83867: Add binding for the CLK_OUT pin muxing option

The DP83867 has a muxing option for the CLK_OUT pin. It is possible
to set CLK_OUT for different channels.
Create a binding to select a specific clock for CLK_OUT pin.

Change-Id: I416afa8ef29d9a684068fa880f99ca7b720cfd14
Signed-off-by: Wadim Egorov <w.egorov@phytec.de>
Signed-off-by: Jacob Chen <jacob2.chen@rock-chips.com>

diff --git a/drivers/net/phy/dp83867.c b/drivers/net/phy/dp83867.c
index f194c0eeedfc8c761494b910297cd30d53dd69db..9f10c06544a27af6d1801457c3032edc3d22d558 100644 (file)
--- a/drivers/net/phy/dp83867.c
+++ b/drivers/net/phy/dp83867.c
@@ -75,6 +75,8 @@
 
 #define DP83867_IO_MUX_CFG_IO_IMPEDANCE_MAX    0x0
 #define DP83867_IO_MUX_CFG_IO_IMPEDANCE_MIN    0x1f
+#define DP83867_IO_MUX_CFG_CLK_O_SEL_MASK      (0x1f << 8)
+#define DP83867_IO_MUX_CFG_CLK_O_SEL_SHIFT     8
 
 /* CFG4 bits */
 #define DP83867_CFG4_PORT_MIRROR_EN              BIT(0)
@@ -91,6 +93,7 @@ struct dp83867_private {
        int fifo_depth;
        int io_impedance;
        int port_mirroring;
+       int clk_output_sel;
 };
 
 static int dp83867_ack_interrupt(struct phy_device *phydev)
@@ -159,6 +162,11 @@ static int dp83867_of_init(struct phy_device *phydev)
        dp83867->io_impedance = -EINVAL;
 
        /* Optional configuration */
+       if (of_property_read_u32(of_node, "ti,clk-output-sel",
+                                &dp83867->clk_output_sel))
+               /* Keep the default value if ti,clk-output-sel is not set */
+               dp83867->clk_output_sel = DP83867_CLK_O_SEL_REF_CLK;
+
        if (of_property_read_bool(of_node, "ti,max-output-impedance"))
                dp83867->io_impedance = DP83867_IO_MUX_CFG_IO_IMPEDANCE_MAX;
        else if (of_property_read_bool(of_node, "ti,min-output-impedance"))
@@ -283,6 +291,14 @@ static int dp83867_config_init(struct phy_device *phydev)
        if (dp83867->port_mirroring != DP83867_PORT_MIRROING_KEEP)
                dp83867_config_port_mirroring(phydev);
 
+       /* Clock output selection */
+       val = phy_read_mmd_indirect(phydev, DP83867_IO_MUX_CFG,
+                                   DP83867_DEVADDR);
+       val &= ~DP83867_IO_MUX_CFG_CLK_O_SEL_MASK;
+       val |= (dp83867->clk_output_sel << DP83867_IO_MUX_CFG_CLK_O_SEL_SHIFT);
+       phy_write_mmd_indirect(phydev, DP83867_IO_MUX_CFG,
+                              DP83867_DEVADDR, val);
+
        return 0;
 }
 

diff --git a/include/dt-bindings/net/ti-dp83867.h b/include/dt-bindings/net/ti-dp83867.h
index 172744a72eb711127defdb007764cc8ecdb27dbb..7b1656427cbe428fd5796d51afe534cd86505918 100644 (file)
--- a/include/dt-bindings/net/ti-dp83867.h
+++ b/include/dt-bindings/net/ti-dp83867.h
@@ -42,4 +42,18 @@
 #define        DP83867_RGMIIDCTL_3_75_NS       0xe
 #define        DP83867_RGMIIDCTL_4_00_NS       0xf
 
+/* IO_MUX_CFG - Clock output selection */
+#define DP83867_CLK_O_SEL_CHN_A_RCLK           0x0
+#define DP83867_CLK_O_SEL_CHN_B_RCLK           0x1
+#define DP83867_CLK_O_SEL_CHN_C_RCLK           0x2
+#define DP83867_CLK_O_SEL_CHN_D_RCLK           0x3
+#define DP83867_CLK_O_SEL_CHN_A_RCLK_DIV5      0x4
+#define DP83867_CLK_O_SEL_CHN_B_RCLK_DIV5      0x5
+#define DP83867_CLK_O_SEL_CHN_C_RCLK_DIV5      0x6
+#define DP83867_CLK_O_SEL_CHN_D_RCLK_DIV5      0x7
+#define DP83867_CLK_O_SEL_CHN_A_TCLK           0x8
+#define DP83867_CLK_O_SEL_CHN_B_TCLK           0x9
+#define DP83867_CLK_O_SEL_CHN_C_TCLK           0xA
+#define DP83867_CLK_O_SEL_CHN_D_TCLK           0xB
+#define DP83867_CLK_O_SEL_REF_CLK              0xC
 #endif