clk: rockchip: add HCLK_USB_PERI for rk3368 usb

Change-Id: Ib1fad4af45ac5ba42ddd97918385aee3bd58e18e
Signed-off-by: Xu Jianqun <jay.xu@rock-chips.com>

diff --git a/drivers/clk/rockchip/clk-rk3368.c b/drivers/clk/rockchip/clk-rk3368.c
index 051ff87b8c31f2bf387eb4a6d4a769edbebd3840..9ff58bf1dfd394d3978ac3f2eee57b9db9c87f7d 100644 (file)
--- a/drivers/clk/rockchip/clk-rk3368.c
+++ b/drivers/clk/rockchip/clk-rk3368.c
@@ -752,7 +752,7 @@ static struct rockchip_clk_branch rk3368_clk_branches[] __initdata = {
        GATE(0, "hclk_mmc_peri", "hclk_peri", CLK_IGNORE_UNUSED, RK3368_CLKGATE_CON(20), 10, GFLAGS),
        GATE(0, "hclk_emem_peri", "hclk_peri", CLK_IGNORE_UNUSED, RK3368_CLKGATE_CON(20), 9, GFLAGS),
        GATE(0, "hclk_peri_ahb_arbi", "hclk_peri", CLK_IGNORE_UNUSED, RK3368_CLKGATE_CON(20), 7, GFLAGS),
-       GATE(0, "hclk_usb_peri", "hclk_peri", CLK_IGNORE_UNUSED, RK3368_CLKGATE_CON(20), 6, GFLAGS),
+       GATE(HCLK_USB_PERI, "hclk_usb_peri", "hclk_peri", CLK_IGNORE_UNUSED, RK3368_CLKGATE_CON(20), 6, GFLAGS),
        GATE(HCLK_HSIC, "hclk_hsic", "hclk_peri", 0, RK3368_CLKGATE_CON(20), 5, GFLAGS),
        GATE(HCLK_HOST1, "hclk_host1", "hclk_peri", CLK_IGNORE_UNUSED, RK3368_CLKGATE_CON(20), 4, GFLAGS),
        GATE(HCLK_HOST0, "hclk_host0", "hclk_peri", 0, RK3368_CLKGATE_CON(20), 3, GFLAGS),

diff --git a/include/dt-bindings/clock/rk3368-cru.h b/include/dt-bindings/clock/rk3368-cru.h
index 2d70733d7ed55cba5650e8a39e45d0ef597bff29..d929b6c53d2875e70ed91725366081eff69f26e7 100644 (file)
--- a/include/dt-bindings/clock/rk3368-cru.h
+++ b/include/dt-bindings/clock/rk3368-cru.h
@@ -157,6 +157,7 @@
 #define PCLK_DPHYTX0           370
 
 /* hclk gates */
+#define HCLK_USB_PERI          447
 #define HCLK_SFC               448
 #define HCLK_OTG0              449
 #define HCLK_HOST0             450