t2Bcc is allowed to have a predicate without a preceding IT instruction.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138946 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/lib/Target/ARM/AsmParser/ARMAsmParser.cpp b/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
index bba09d4674bda02f0a3f9cd9f56c98234e2f5596..f71d0f8642c8ade3bf07ec8e6e25c8c2cfb4d5e1 100644 (file)
--- a/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
+++ b/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
@@ -3377,7 +3377,8 @@ validateInstruction(MCInst &Inst,
   // Check for non-'al' condition codes outside of the IT block.
   } else if (isThumbTwo() && MCID.isPredicable() &&
              Inst.getOperand(MCID.findFirstPredOperandIdx()).getImm() !=
-             ARMCC::AL && Inst.getOpcode() != ARM::tBcc)
+             ARMCC::AL && Inst.getOpcode() != ARM::tBcc &&
+             Inst.getOpcode() != ARM::t2Bcc)
     return Error(Loc, "predicated instructions must be in IT block");
 
   switch (Inst.getOpcode()) {

diff --git a/test/MC/ARM/basic-thumb2-instructions.s b/test/MC/ARM/basic-thumb2-instructions.s
index 492687ea40c491a468983c64aa3c60b5e8033fb0..4641fe3d37f066d05b7069deb04ea1b3830ea80e 100644 (file)
--- a/test/MC/ARM/basic-thumb2-instructions.s
+++ b/test/MC/ARM/basic-thumb2-instructions.s
@@ -86,6 +86,12 @@ _func:
 @ CHECK: addw  r12, r6, #256           @ encoding: [0x06,0xf2,0x00,0x1c]
 @ CHECK: adds.w        r1, r2, #496            @ encoding: [0x12,0xf5,0xf8,0x71]
 
+@------------------------------------------------------------------------------
+@ B
+@------------------------------------------------------------------------------
+        bmi.w   #-183396
+
+@ CHECK: bmi.w   #-183396                @ encoding: [0x13,0xf5,0xce,0xa9]
 
 @------------------------------------------------------------------------------
 @ CBZ/CBNZ