Add FSQRT, FSIN, FCOS nodes, patch contributed by Morten Ofstad

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@21605 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/include/llvm/CodeGen/SelectionDAGNodes.h b/include/llvm/CodeGen/SelectionDAGNodes.h
index 1df651381c14afbda8f6ac78250474ea5e418127..f3be3344a9f1e094a800d7a90e423562cc2feab6 100644 (file)
--- a/include/llvm/CodeGen/SelectionDAGNodes.h
+++ b/include/llvm/CodeGen/SelectionDAGNodes.h
@@ -168,9 +168,9 @@ namespace ISD {
     // FP_EXTEND - Extend a smaller FP type into a larger FP type.
     FP_EXTEND,
 
-    // FNEG, FABS - Perform unary floating point negation and absolute value
-    // operations.
-    FNEG, FABS,
+    // FNEG, FABS, FSQRT, FSIN, FCOS - Perform unary floating point negation,
+    // absolute value, square root, sine and cosine operations.
+    FNEG, FABS, FSQRT, FSIN, FCOS,
 
     // Other operators.  LOAD and STORE have token chains as their first
     // operand, then the same operands as an LLVM load/store instruction.

diff --git a/lib/CodeGen/SelectionDAG/SelectionDAG.cpp b/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
index 2a88270965460127c8dadf5e7fc907eaec3c1f12..f9b347d4c938a6c917efbe3ad60835d1afcf8076 100644 (file)
--- a/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
+++ b/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
@@ -1568,6 +1568,9 @@ const char *SDNode::getOperationName() const {
   // Unary operators
   case ISD::FABS:   return "fabs";
   case ISD::FNEG:   return "fneg";
+  case ISD::FSQRT:  return "fsqrt";
+  case ISD::FSIN:   return "fsin";
+  case ISD::FCOS:   return "fcos";
 
   // Binary operators
   case ISD::ADD:    return "add";
@@ -1593,7 +1596,7 @@ const char *SDNode::getOperationName() const {
   case ISD::SRA_PARTS:   return "sra_parts";
   case ISD::SRL_PARTS:   return "srl_parts";
 
-    // Conversion operators.
+  // Conversion operators.
   case ISD::SIGN_EXTEND: return "sign_extend";
   case ISD::ZERO_EXTEND: return "zero_extend";
   case ISD::SIGN_EXTEND_INREG: return "sign_extend_inreg";