x86/amd-iommu: Export cache-coherency capability

This patch exports the capability of the AMD IOMMU to force
cache coherency of DMA transactions through the IOMMU-API.
This is required to disable some nasty hacks in KVM when
this capability is not available.

Signed-off-by: Joerg Roedel <joerg.roedel@amd.com>

diff --git a/arch/x86/kernel/amd_iommu.c b/arch/x86/kernel/amd_iommu.c
index 29dd3b9f2f0919ea85a14b578a7d6009552570ea..fa044e1e30a2ed081175480dccec352a7e381392 100644 (file)
--- a/arch/x86/kernel/amd_iommu.c
+++ b/arch/x86/kernel/amd_iommu.c
@@ -2572,6 +2572,11 @@ static phys_addr_t amd_iommu_iova_to_phys(struct iommu_domain *dom,
 static int amd_iommu_domain_has_cap(struct iommu_domain *domain,
                                    unsigned long cap)
 {
+       switch (cap) {
+       case IOMMU_CAP_CACHE_COHERENCY:
+               return 1;
+       }
+
        return 0;
 }