.width = 129,
.height = 171,
},
+ .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
};
static const struct drm_display_mode lg_lp097qx1_spa1_mode = {
struct drm_connector_state *conn_state)
{
struct rockchip_crtc_state *s = to_rockchip_crtc_state(crtc_state);
+ struct drm_connector *connector = conn_state->connector;
+ struct drm_display_info *info = &connector->display_info;
/*
* The hardware IC designed that VOP must output the RGB10 video
*/
s->output_mode = ROCKCHIP_OUT_MODE_AAAA;
s->output_type = DRM_MODE_CONNECTOR_eDP;
+ if (info->num_bus_formats)
+ s->bus_format = info->bus_formats[0];
return 0;
}
{
struct rockchip_crtc_state *s = to_rockchip_crtc_state(crtc_state);
struct dw_mipi_dsi *dsi = encoder_to_dsi(encoder);
+ struct drm_connector *connector = conn_state->connector;
+ struct drm_display_info *info = &connector->display_info;
switch (dsi->format) {
case MIPI_DSI_FMT_RGB888:
}
s->output_type = DRM_MODE_CONNECTOR_DSI;
+ if (info->num_bus_formats)
+ s->bus_format = info->bus_formats[0];
return 0;
}
s->output_mode = ROCKCHIP_OUT_MODE_AAAA;
s->output_type = DRM_MODE_CONNECTOR_HDMIA;
+ s->bus_format = MEDIA_BUS_FMT_RGB888_1X24;
return 0;
}
s->output_mode = ROCKCHIP_OUT_MODE_P888;
s->output_type = DRM_MODE_CONNECTOR_HDMIA;
+ s->bus_format = MEDIA_BUS_FMT_RGB888_1X24;
return 0;
}
int dsp_layer_sel;
int output_type;
int output_mode;
+ int bus_format;
};
#define to_rockchip_crtc_state(s) \
s->output_mode = ROCKCHIP_OUT_MODE_P888;
VOP_CTRL_SET(vop, out_mode, s->output_mode);
+ switch (s->bus_format) {
+ case MEDIA_BUS_FMT_RGB565_1X16:
+ val = DITHER_DOWN_EN(1) | DITHER_DOWN_MODE(RGB888_TO_RGB565) |
+ PRE_DITHER_DOWN_EN(1);
+ break;
+ case MEDIA_BUS_FMT_RGB666_1X18:
+ case MEDIA_BUS_FMT_RGB666_1X24_CPADHI:
+ val = DITHER_DOWN_EN(1) | DITHER_DOWN_MODE(RGB888_TO_RGB666) |
+ PRE_DITHER_DOWN_EN(1);
+ break;
+ case MEDIA_BUS_FMT_RGB888_1X24:
+ default:
+ val = DITHER_DOWN_EN(0) | PRE_DITHER_DOWN_EN(0);
+ break;
+ }
+ val |= DITHER_DOWN_MODE_SEL(DITHER_DOWN_ALLEGRO);
+ VOP_CTRL_SET(vop, dither_down, val);
VOP_CTRL_SET(vop, htotal_pw, (htotal << 16) | hsync_len);
val = hact_st << 16;
SCALE_DOWN_AVG = 0x1
};
+enum dither_down_mode {
+ RGB888_TO_RGB565 = 0x0,
+ RGB888_TO_RGB666 = 0x1
+};
+
+enum dither_down_mode_sel {
+ DITHER_DOWN_ALLEGRO = 0x0,
+ DITHER_DOWN_FRC = 0x1
+};
+
+#define PRE_DITHER_DOWN_EN(x) ((x) << 0)
+#define DITHER_DOWN_EN(x) ((x) << 1)
+#define DITHER_DOWN_MODE(x) ((x) << 2)
+#define DITHER_DOWN_MODE_SEL(x) ((x) << 3)
#define FRAC_16_16(mult, div) (((mult) << 16) / (div))
#define SCL_FT_DEFAULT_FIXPOINT_SHIFT 12
#define SCL_MAX_VSKIPLINES 4
struct drm_connector_state *conn_state)
{
struct rockchip_crtc_state *s = to_rockchip_crtc_state(crtc_state);
+ struct drm_connector *connector = conn_state->connector;
+ struct drm_display_info *info = &connector->display_info;
s->output_mode = ROCKCHIP_OUT_MODE_P888;
s->output_type = DRM_MODE_CONNECTOR_LVDS;
+ if (info->num_bus_formats)
+ s->bus_format = info->bus_formats[0];
return 0;
}