rk32 dp: fix edid&dpcd access

diff --git a/drivers/video/rockchip/transmitter/rk32_dp.c b/drivers/video/rockchip/transmitter/rk32_dp.c
index 4123be1b0126e9e7084b93592d3fec7f868c8596..e7e4f6b1d87ba869800f33dccf8d1b5b62cf0b41 100644 (file)
--- a/drivers/video/rockchip/transmitter/rk32_dp.c
+++ b/drivers/video/rockchip/transmitter/rk32_dp.c
@@ -52,6 +52,7 @@ static int rk32_edp_init_edp(struct rk32_edp *edp)
 
        val = 0x80008000;
        writel_relaxed(val, RK_CRU_VIRT + 0x0d0);
+       
        rk32_edp_reset(edp);
        rk32_edp_init_refclk(edp);
        rk32_edp_init_interrupt(edp);
@@ -200,7 +201,7 @@ static int rk32_edp_read_edid(struct rk32_edp *edp)
                        }
                }
        }
-
+       fb_edid_to_monspecs(edid, &edp->specs);
        dev_err(edp->dev, "EDID Read success!\n");
        return 0;
 }
@@ -216,6 +217,8 @@ static int rk32_edp_handle_edid(struct rk32_edp *edp)
        if (retval < 0)
                return retval;
 
+       for (i=0 ;i < 12; i++)
+               dev_info(edp->dev, "%d:>>0x%02x\n", i, buf[i]);
        /* Read EDID */
        for (i = 0; i < 3; i++) {
                retval = rk32_edp_read_edid(edp);
@@ -1086,7 +1089,7 @@ edp_phy_init:
        
        rk32_edp_init_edp(edp);
 
-       /*ret = rk32_edp_handle_edid(edp);
+       ret = rk32_edp_handle_edid(edp);
        if (ret) {
                dev_err(edp->dev, "unable to handle edid\n");
                //goto out;
@@ -1104,10 +1107,10 @@ edp_phy_init:
                dev_err(edp->dev, "unable to set enhanced mode\n");
                //goto out;
        }
-       rk32_edp_enable_enhanced_mode(edp, 0);*/
+       rk32_edp_enable_enhanced_mode(edp, 0);
 
        /* Link Training */
-       ret = rk32_edp_set_link_train(edp, LANE_CNT4, LINK_RATE_2_70GBPS);
+       ret = rk32_edp_set_link_train(edp, LANE_CNT4, LINK_RATE_1_62GBPS);
        if (ret) {
                dev_err(edp->dev, "link train failed\n");
                //goto out;

diff --git a/drivers/video/rockchip/transmitter/rk32_dp.h b/drivers/video/rockchip/transmitter/rk32_dp.h
index 8a3325d8f0351229edb9158f937677d635422b2a..2bfae746bbdb545dc18fc7329967c4b870531116 100644 (file)
--- a/drivers/video/rockchip/transmitter/rk32_dp.h
+++ b/drivers/video/rockchip/transmitter/rk32_dp.h
@@ -95,7 +95,7 @@
 #define DP_BIAS                                        0x124
 
 #define PLL_REG_1                              0xfc
-#define REF_CLK_24M                            (0x01 << 1)
+#define REF_CLK_24M                            (0x1 << 1)
 #define REF_CLK_27M                            (0x0 << 1)
 
 #define PLL_REG_2                              0x9e4
@@ -513,6 +513,7 @@ struct rk32_edp {
        struct link_train       link_train;
        struct video_info       video_info;
        struct rk_screen        screen;
+       struct fb_monspecs      specs;
        int                     enabled;
 };
 

diff --git a/drivers/video/rockchip/transmitter/rk32_dp_reg.c b/drivers/video/rockchip/transmitter/rk32_dp_reg.c
index 944b00f98e617ba70a6f49a0a937378186917f71..f8e3db775d7d77dac6fe8f6b5ee0b4cc74c3b466 100644 (file)
--- a/drivers/video/rockchip/transmitter/rk32_dp_reg.c
+++ b/drivers/video/rockchip/transmitter/rk32_dp_reg.c
@@ -75,7 +75,7 @@ void rk32_edp_init_refclk(struct rk32_edp *edp)
 
        val = SEL_24M;
        writel(val, edp->regs + ANALOG_CTL_2);
-       
+
        val = REF_CLK_24M;
        writel(val, edp->regs + PLL_REG_1);
 
@@ -95,7 +95,7 @@ void rk32_edp_init_refclk(struct rk32_edp *edp)
        writel(val, edp->regs + SSC_REG);
        val = 0x87;
        writel(val, edp->regs + TX_REG_COMMON);
-       val = 0x03;
+       val = 0x13;
        writel(val, edp->regs + DP_AUX);
        val = 0x46;
        writel(val, edp->regs + DP_BIAS);
@@ -175,7 +175,12 @@ void rk32_edp_reset(struct rk32_edp *edp)
        u32 val;
 
        //writel(RST_DP_TX, edp->regs + TX_SW_RST);
-
+       /*val = 0x80008000;
+       writel_relaxed(val, RK_CRU_VIRT + 0x01d0);
+       mdelay(12);
+       val = 0x80000000;
+       writel_relaxed(val, RK_CRU_VIRT + 0x01d0);
+       mdelay(12);*/
        rk32_edp_stop_video(edp);
        rk32_edp_enable_video_mute(edp, 0);
 
@@ -306,7 +311,7 @@ void rk32_edp_init_hpd(struct rk32_edp *edp)
        writel(val, edp->regs + DP_INT_STA);
 
        val = readl(edp->regs + SYS_CTL_3);
-       val &= ~(F_HPD | HPD_CTRL);
+       val |= (F_HPD | HPD_CTRL);
        writel(val, edp->regs + SYS_CTL_3);
 }
 
@@ -1020,8 +1025,8 @@ int rk32_edp_init_video(struct rk32_edp *edp)
        val = CHA_CRI(4) | CHA_CTRL;
        writel(val, edp->regs + SYS_CTL_2);
 
-       val = 0x0;
-       writel(val, edp->regs + SYS_CTL_3);
+       //val = 0x0;
+       //writel(val, edp->regs + SYS_CTL_3);
 
        val = VID_HRES_TH(2) | VID_VRES_TH(0);
        writel(val, edp->regs + VIDEO_CTL_8);