switch (Node->getOpcode()) {
case ISD::UDIV:
case ISD::SDIV:
- if (VT == MVT::i32) {
- LC = Node->getOpcode() == ISD::UDIV
- ? RTLIB::UDIV_I32 : RTLIB::SDIV_I32;
- isSigned = Node->getOpcode() == ISD::SDIV;
- }
- break;
+ isSigned = Node->getOpcode() == ISD::SDIV;
+ if (VT == MVT::i16)
+ LC = (isSigned ? RTLIB::SDIV_I16 : RTLIB::UDIV_I16);
+ else if (VT == MVT::i32)
+ LC = (isSigned ? RTLIB::SDIV_I32 : RTLIB::UDIV_I32);
+ else if (VT == MVT::i64)
+ LC = (isSigned ? RTLIB::SDIV_I64 : RTLIB::UDIV_I64);
+ else if (VT == MVT::i128)
+ LC = (isSigned ? RTLIB::SDIV_I128 : RTLIB::UDIV_I128);
+ break;
case ISD::MUL:
if (VT == MVT::i16)
LC = RTLIB::MUL_I16;
- if (VT == MVT::i32)
+ else if (VT == MVT::i32)
LC = RTLIB::MUL_I32;
else if (VT == MVT::i64)
LC = RTLIB::MUL_I64;
Names[RTLIB::MUL_I32] = "__mulsi3";
Names[RTLIB::MUL_I64] = "__muldi3";
Names[RTLIB::MUL_I128] = "__multi3";
+ Names[RTLIB::SDIV_I16] = "__divhi3";
Names[RTLIB::SDIV_I32] = "__divsi3";
Names[RTLIB::SDIV_I64] = "__divdi3";
Names[RTLIB::SDIV_I128] = "__divti3";
+ Names[RTLIB::UDIV_I32] = "__udivhi3";
Names[RTLIB::UDIV_I32] = "__udivsi3";
Names[RTLIB::UDIV_I64] = "__udivdi3";
Names[RTLIB::UDIV_I128] = "__udivti3";
+ Names[RTLIB::SREM_I16] = "__modhi3";
Names[RTLIB::SREM_I32] = "__modsi3";
Names[RTLIB::SREM_I64] = "__moddi3";
Names[RTLIB::SREM_I128] = "__modti3";
+ Names[RTLIB::UREM_I16] = "__umodsi3";
Names[RTLIB::UREM_I32] = "__umodsi3";
Names[RTLIB::UREM_I64] = "__umoddi3";
Names[RTLIB::UREM_I128] = "__umodti3";