* Note: The FPGA configuration supports a maximum of 12 host channels.
*/
int32_t host_channels;
-#define dwc_param_host_channels_default 12
+#define dwc_param_host_channels_default 16
/** The number of endpoints in addition to EP0 available for device
* mode operations.
cru_set_soft_reset(SOFT_RST_USB_HOST_2_0_PHY, false);
cru_set_soft_reset(SOFT_RST_USB_HOST_2_0_CONTROLLER, false);
#endif
+#ifdef CONFIG_ARCH_RK30
+ *(unsigned int*)(USBGRF_UOC1_CON2+4) = ((1<<5)|((1<<5)<<16));
+#endif
if (dwc_otg_device == 0)
{
dev_err(dev, "kmalloc of dwc_otg_device failed\n");
return;
}
-
#ifdef DEBUG
static void dump_urb_info(struct urb *_urb, char* _fn_name)
{
return retval;
}
#endif
-#if 1
- /*
- * Make sure the start of frame interrupt is enabled now that
- * we know we should have queued data. The SOF interrupt
- * handler automatically disables itself when idle to reduce
- * the number of interrupts. See dwc_otg_hcd_handle_sof_intr()
- * for the disable
- */
- dwc_modify_reg32(&dwc_otg_hcd->core_if->core_global_regs->gintmsk, 0,
- DWC_SOF_INTR_MASK);
-#endif
#ifdef DEBUG
if (CHK_DEBUG_LEVEL(DBG_HCDV | DBG_HCD_URB)) {
dump_urb_info(_urb, "dwc_otg_hcd_urb_enqueue");
"Error status %d\n", retval);
dwc_otg_hcd_qtd_free(qtd);
}
+#if 1
+ /*
+ * Make sure the start of frame interrupt is enabled now that
+ * we know we should have queued data. The SOF interrupt
+ * handler automatically disables itself when idle to reduce
+ * the number of interrupts. See dwc_otg_hcd_handle_sof_intr()
+ * for the disable
+ */
+ dwc_modify_reg32(&dwc_otg_hcd->core_if->core_global_regs->gintmsk, 0,
+ DWC_SOF_INTR_MASK);
+#endif
out:
return retval;
pcd->vbus_status = 0;
pcd->phy_suspend = 0;
if(dwc_otg_is_device_mode(core_if))
- mod_timer(&pcd->check_vbus_timer, jiffies+(HZ<<2)); // delay 16 S +(HZ<<4)
+ mod_timer(&pcd->check_vbus_timer, jiffies+(HZ<<4)); // delay 16 S
DWC_PRINT("%s pass,everest\n", __func__);
// dwc_otg_pcd_start_vbus_timer( pcd );
return 0;