Return the base register of a register list for the "getReg()" method. This is

to satisfy the ClassifyOperand method of the Asm matcher without having to add a
RegList type to every back-end.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118360 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/lib/Target/ARM/AsmParser/ARMAsmParser.cpp b/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
index 71191f7cf413dbcb2da8a349f7994895dbc9644a..1744899a29b1812f6464bf4b33af886875ad4a41 100644 (file)
--- a/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
+++ b/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
@@ -129,7 +129,7 @@ class ARMOperand : public MCParsedAsmOperand {
       bool Writeback;
     } Reg;
 
-     struct {
+    struct {
       unsigned RegStart;
       unsigned Number;
     } RegList;
@@ -198,8 +198,13 @@ public:
   }
 
   unsigned getReg() const {
-    assert(Kind == Register && "Invalid access!");
-    return Reg.RegNum;
+    assert((Kind == Register || Kind == RegisterList) && "Invalid access!");
+    unsigned RegNum = 0;
+    if (Kind == Register)
+      RegNum = Reg.RegNum;
+    else
+      RegNum = RegList.RegStart;
+    return RegNum;
   }
 
   std::pair<unsigned, unsigned> getRegList() const {