emitJumpTableAddress(MO.getIndex(), ARM::reloc_arm_relative);
else if (MO.isMBB())
emitMachineBasicBlock(MO.getMBB(), ARM::reloc_arm_branch);
- else {
-#ifndef NDEBUG
- errs() << MO;
-#endif
- llvm_unreachable(0);
- }
+ else
+ llvm_unreachable("Unable to encode MachineOperand!");
return 0;
}
[(ARMcall GPR:$func)]>,
Requires<[IsARM, HasV5T, IsNotDarwin]> {
bits<4> func;
- let Inst{27-4} = 0b000100101111111111110011;
+ let Inst{31-4} = 0b1110000100101111111111110011;
let Inst{3-0} = func;
}
// ARMv4T
// Note: Restrict $func to the tGPR regclass to prevent it being in LR.
+ // FIXME: x2 insn patterns like this need to be pseudo instructions.
def BX : ABXIx2<(outs), (ins tGPR:$func, variable_ops),
IIC_Br, "mov\tlr, pc\n\tbx\t$func",
[(ARMcall_nolink tGPR:$func)]>,
IIC_Br, "blx\t$func",
[(ARMcall GPR:$func)]>, Requires<[IsARM, HasV5T, IsDarwin]> {
bits<4> func;
- let Inst{27-4} = 0b000100101111111111110011;
+ let Inst{31-4} = 0b1110000100101111111111110011;
let Inst{3-0} = func;
}
.bitcastToAPInt().getHiBits(32).getLimitedValue());
}
-#ifndef NDEBUG
- errs() << MO;
-#endif
- llvm_unreachable(0);
+ llvm_unreachable("Unable to encode MCOperand!");
return 0;
}
}
Fixups.push_back(MCFixup::Create(0, Expr, Kind));
return 0;
- }
- llvm_unreachable("Unsupported MCExpr type in MCOperand");
+ };
+ llvm_unreachable("Unsupported MCExpr type in MCOperand!");
return 0;
}