\r
#include <mach/rk29_iomap.h>\r
#include <mach/cru.h>\r
+#include <mach/memory.h>\r
+#include <mach/sram.h>\r
+#include <linux/clk.h>\r
+\r
+#include <asm/delay.h>\r
+#include <asm/tlbflush.h>\r
+#include <asm/cacheflush.h>\r
\r
#define cru_readl(offset) readl(RK29_CRU_BASE + offset)\r
#define cru_writel(v, offset) do { writel(v, RK29_CRU_BASE + offset); readl(RK29_CRU_BASE + offset); } while (0)\r
barrier();\r
}\r
\r
-static void pwm2gpiodefault(void)\r
+\r
+#if 0\r
+volatile int testflag;\r
+static void __rk29_reset_to_maskrom(void)\r
+{\r
+ u32 reg;\r
+ asm("mrc p15, 0, %0, c1, c0, 0\n\t"\r
+ "bic %0, %0, #(1 << 13) @set vector to 0x00000000\n\t"\r
+ "bic %0, %0, #(1 << 0) @disable mmu\n\t"\r
+ "bic %0, %0, #(1 << 12) @disable I CACHE\n\t"\r
+ "bic %0, %0, #(1 << 2) @disable D DACHE\n\t"\r
+ "bic %0, %0, #(1 << 11) @disable \n\t"\r
+ "bic %0, %0, #(1 << 28) @disable \n\t"\r
+ "mcr p15, 0, %0, c1, c0, 0\n\t"\r
+ // "mcr p15, 0, %0, c8, c7, 0 @ invalidate whole TLB\n\t"\r
+ // "mcr p15, 0, %0, c7, c5, 6 @ invalidate BTC\n\t"\r
+ : "=r" (reg));\r
+\r
+ asm("b 1f\n\t"\r
+ ".align 5\n\t"\r
+ "1:\n\t"\r
+ "mcr p15, 0, %0, c7, c10, 5\n\t"\r
+ "mcr p15, 0, %0, c7, c10, 4\n\t"\r
+ "mov pc, #0" : : "r" (reg));\r
+} \r
+#endif\r
+\r
+static void pwm2gpiodefault(void)\r
{\r
#define REG_FILE_BASE_ADDR RK29_GRF_BASE\r
volatile unsigned int * pGRF_GPIO2L_IOMUX = (volatile unsigned int *)(REG_FILE_BASE_ADDR + 0x58);\r
*pGRF_GPIO2L_IOMUX &= ~(0x3<<6);\r
// set gpio to input\r
*pGPIO2_DIR &= ~(0x1<<3);\r
+// testflag =1;\r
} \r
\r
\r
-void rk29_arch_reset(int mode, const char *cmd)\r
+extern void __rb( void* );\r
+void rb( void )\r
+{\r
+ void(*cb)(void* ) ;\r
+ \r
+ void * uart_base = (unsigned int *)ioremap( RK29_UART1_PHYS , RK29_UART1_SIZE );\r
+ local_irq_disable();\r
+ cb = (void(*)(void* ))__pa(__rb);\r
+ __cpuc_flush_kern_all();\r
+ __cpuc_flush_user_all();\r
+ //printk("begin to jump to reboot,uart1 va=0x%p\n" , uart_base);\r
+ //while(testflag); \r
+ cb( uart_base );\r
+}\r
+\r
+void rk29_arch_reset(int mode, const char *cmd)\r
{\r
u32 reg;\r
\r
\r
local_irq_disable();\r
local_fiq_disable();\r
- \r
pwm2gpiodefault();\r
\r
cru_writel((cru_readl(CRU_MODE_CON) & ~CRU_CPU_MODE_MASK) | CRU_CPU_MODE_SLOW, CRU_MODE_CON);\r
writel(0, RK29_CPU_AXI_BUS0_PHYS);\r
writel(0, RK29_AXI1_PHYS);\r
\r
- __cpuc_flush_kern_all();\r
- __cpuc_flush_user_all();\r
-\r
- asm("mrc p15, 0, %0, c1, c0, 0\n\t"\r
- "bic r0, %0, #(1 << 13) @set vector to 0x00000000\n\t"\r
- "bic r0, %0, #(1 << 0) @disable mmu\n\t"\r
- "bic r0, %0, #(1 << 12) @disable I CACHE\n\t"\r
- "bic r0, %0, #(1 << 2) @disable D DACHE\n\t"\r
- "bic r0, %0, #(1 << 11) @disable \n\t"\r
- "bic r0, %0, #(1 << 28) @disable \n\t"\r
- "mcr p15, 0, %0, c1, c0, 0\n\t"\r
-// "mcr p15, 0, %0, c8, c7, 0 @ invalidate whole TLB\n\t"\r
-// "mcr p15, 0, %0, c7, c5, 6 @ invalidate BTC\n\t"\r
- : "=r" (reg));\r
-\r
- asm("b 1f\n\t"\r
- ".align 5\n\t"\r
- "1:\n\t"\r
- "mcr p15, 0, %0, c7, c10, 5\n\t"\r
- "mcr p15, 0, %0, c7, c10, 4\n\t"\r
- "mov pc, #0" : : "r" (reg));\r
+ //__cpuc_flush_kern_all();\r
+ //__cpuc_flush_user_all();\r
+ \r
+ rb();\r
+\r
}\r
\r
\r
#include <asm/ptrace.h>
#include <asm/assembler.h>
#include <asm/asm-offsets.h>
+#include <mach/rk29_iomap.h>
#__scu_call_wrap:
#
ldr r0, [r12, #S_PSR]
msr spsr_cxsf, r0
ldmia r12, {r0 - pc}^ @ load r0 - pc, cpsr
+
+ENTRY(__run)
+ mov r0, r0
+ mov pc, lr
+
+
+/* 20110212,HSL@RK, USE parm0 for debug.
+ *
+ */
+ENTRY(__rb)
+ mov r7,r0
+/* adr r0 , __rb_info
+ adr r8, __prk
+ ldr r8,[r8,#0]
+ adr r1 , __rb
+ mov lr , pc
+ bx r8
+ mov r0,#0x10000
+ bl __rb_delay
+*/
+ mov r8,r7
+/* adr r0 , __prk_info
+1:
+ ldrb r1,[r0],#1
+ cmp r1,#0
+ strne r1,[r8,#0]
+ bne 1b
+ mov r0,#0x20000
+ bl __rb_delay*/
+
+ MRC p15,0,r0,c1,c0,0
+ BIC r0,r0,#(1<<0) @disable mmu
+ BIC r0,r0,#(1<<13) @set vector to 0x00000000
+ BIC r0,r0,#(1<<12) @disable I CACHE
+ BIC r0,r0,#(1<<2) @disable D DACHE
+ BIC r0,r0,#(1<<11) @disable Z
+ BIC r0,r0,#(1<<28) @disable TRE
+ MCR p15,0,r0,c1,c0,0
+ isb
+ dsb
+ nop
+ nop
+ nop
+
+ adr r7,__regs
+
+ ldr r8,[r7,#0x10]
+/* adr r3 , __dbg_info
+2:
+ ldrb r1,[r3],#1
+ cmp r1,#0
+ strne r1,[r8,#0]
+ bne 2b
+
+ mov r0,#0x20000
+ bl __rb_delay*/
+
+wait:
+ @b wait
+ @arm slow mod.
+ ldr r8,[r7,#0xc]
+ ldr r9,[r8,#0]
+ bic r9,r9,#3
+ str r9,[r8,#0]
+ dsb
+ mov r0,#0x10000
+ bl __rb_delay
+
+ @ unremap, and axi.
+ ldr r8,[r7,#0]
+ ldr r9,[r8,#0]
+ bic r9,r9,#(1<<21)
+ str r9,[r8,#0]
+
+ mov r9,#0
+ ldr r8,[r7,#4]
+ str r9,[r8,#0]
+
+ ldr r8,[r7,#8]
+ str r9,[r8,#0]
+ dsb
+
+
+ ldr r8,[r7,#0x10]
+/* adr r0 , __dbg_info1
+3:
+ ldrb r1,[r0],#1
+ cmp r1,#0
+ strne r1,[r8,#0]
+ bne 3b
+
+ mov r0,#0x10000
+ bl __rb_delay
+*/
+ mov r4, #0
+ mov pc, r4
+
+__prk:
+ .long printk
+__rb_info:
+ .asciz "at reboot function,pc=0x%x\n"
+__prk_info:
+ .asciz "after printk!\n\r"
+__dbg_info:
+ .asciz "AFTER DIS MMU\n\r"
+__dbg_info1:
+ .asciz "LAST JUMP TO 0\n\r"
+ .align
+__regs:
+ .long RK29_GRF_PHYS+0xc0 @ 0x20008000 , unremap
+ .long RK29_CPU_AXI_BUS0_PHYS @ 0x15000000
+ .long RK29_AXI1_PHYS @ 0x10000000
+ .long RK29_CRU_PHYS @ 0x20000000
+ .long RK29_UART1_PHYS @ 0x20060000 , printk for debug.
+ .align
+
+__rb_delay:
+ subs r0, r0, #1
+ bhi __rb_delay
+ mov pc, lr
#if FIQ_ENABLE
.align
projects / firefly-linux-kernel-4.4.55.git / commitdiff