arm64: dts: rockchip: rk3368: add qos node

when pd power on/off, the qos regs need to save and restore.

Change-Id: I34146660e75609517463d679271386b536401b20
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>

diff --git a/arch/arm64/boot/dts/rockchip/rk3368.dtsi b/arch/arm64/boot/dts/rockchip/rk3368.dtsi
index 6ba70c28a8e8fe832dad15c4352a5d60a9e4ad5b..37238b8e63dea3c82162d3887b7bff0286684e52 100644 (file)
--- a/arch/arm64/boot/dts/rockchip/rk3368.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3368.dtsi
@@ -846,6 +846,71 @@
                status = "disabled";
        };
 
+       qos_iep: qos@ffad0000 {
+               compatible = "syscon";
+               reg = <0x0 0xffad0000 0x0 0x20>;
+       };
+
+       qos_isp_r0: qos@ffad0080 {
+               compatible = "syscon";
+               reg = <0x0 0xffad0080 0x0 0x20>;
+       };
+
+       qos_isp_r1: qos@ffad0100 {
+               compatible = "syscon";
+               reg = <0x0 0xffad0100 0x0 0x20>;
+       };
+
+       qos_isp_w0: qos@ffad0180 {
+               compatible = "syscon";
+               reg = <0x0 0xffad0180 0x0 0x20>;
+       };
+
+       qos_isp_w1: qos@ffad0200 {
+               compatible = "syscon";
+               reg = <0x0 0xffad0200 0x0 0x20>;
+       };
+
+       qos_vip: qos@ffad0280 {
+               compatible = "syscon";
+               reg = <0x0 0xffad0280 0x0 0x20>;
+       };
+
+       qos_vop: qos@ffad0300 {
+               compatible = "syscon";
+               reg = <0x0 0xffad0300 0x0 0x20>;
+       };
+
+       qos_rga_r: qos@ffad0380 {
+               compatible = "syscon";
+               reg = <0x0 0xffad0380 0x0 0x20>;
+       };
+
+       qos_rga_w: qos@ffad0400 {
+               compatible = "syscon";
+               reg = <0x0 0xffad0400 0x0 0x20>;
+       };
+
+       qos_hevc_r: qos@ffae0000 {
+               compatible = "syscon";
+               reg = <0x0 0xffae0000 0x0 0x20>;
+       };
+
+       qos_vpu_r: qos@ffae0100 {
+               compatible = "syscon";
+               reg = <0x0 0xffae0100 0x0 0x20>;
+       };
+
+       qos_vpu_w: qos@ffae0180 {
+               compatible = "syscon";
+               reg = <0x0 0xffae0180 0x0 0x20>;
+       };
+
+       qos_gpu: qos@ffaf0000 {
+               compatible = "syscon";
+               reg = <0x0 0xffaf0000 0x0 0x20>;
+       };
+
        pmu: power-management@ff730000 {
                compatible = "rockchip,rk3368-pmu", "syscon", "simple-mfd";
                reg = <0x0 0xff730000 0x0 0x1000>;
@@ -912,6 +977,15 @@
                                         <&cru SCLK_RGA>,
                                         <&cru SCLK_HDMI_CEC>,
                                         <&cru SCLK_HDMI_HDCP>;
+                               pm_qos = <&qos_iep>,
+                                        <&qos_isp_r0>,
+                                        <&qos_isp_r1>,
+                                        <&qos_isp_w0>,
+                                        <&qos_isp_w1>,
+                                        <&qos_vip>,
+                                        <&qos_vop>,
+                                        <&qos_rga_r>,
+                                        <&qos_rga_w>;
                        };
                        /*
                         * Note: ACLK_VCODEC/HCLK_VCODEC are VCODEC
@@ -924,6 +998,9 @@
                                         <&cru HCLK_VIDEO>,
                                         <&cru SCLK_HEVC_CABAC>,
                                         <&cru SCLK_HEVC_CORE>;
+                               pm_qos = <&qos_hevc_r>,
+                                        <&qos_vpu_r>,
+                                        <&qos_vpu_w>;
                        };
                        /*
                         * Note: ACLK_GPU is the GPU clock,
@@ -934,6 +1011,7 @@
                                clocks = <&cru ACLK_GPU_CFG>,
                                         <&cru ACLK_GPU_MEM>,
                                         <&cru SCLK_GPU_CORE>;
+                               pm_qos = <&qos_gpu>;
                        };
                };
        };