Fix decoding of Thumb2 prefetch instructions, which account for all the remaining...

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138341 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/lib/Target/ARM/Disassembler/ARMDisassembler.cpp b/lib/Target/ARM/Disassembler/ARMDisassembler.cpp
index 5711b69796e0c1c2875012b966bd869dab9381ae..c4b2f613cc7b8e65b2e465c85f6b59451be98b22 100644 (file)
--- a/lib/Target/ARM/Disassembler/ARMDisassembler.cpp
+++ b/lib/Target/ARM/Disassembler/ARMDisassembler.cpp
@@ -2392,9 +2392,15 @@ static DecodeStatus DecodeT2LoadShift(llvm::MCInst &Inst, unsigned Insn,
                               uint64_t Address, const void *Decoder) {
   DecodeStatus S = Success;
 
-  if (Inst.getOpcode() != ARM::t2PLDs) {
-    unsigned Rt = fieldFromInstruction32(Insn, 12, 4);
-    CHECK(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder));
+  switch (Inst.getOpcode()) {
+    case ARM::t2PLDs:
+    case ARM::t2PLDWs:
+    case ARM::t2PLIs:
+      break;
+    default: {
+      unsigned Rt = fieldFromInstruction32(Insn, 12, 4);
+      CHECK(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder));
+    }
   }
 
   unsigned Rn = fieldFromInstruction32(Insn, 16, 4);

diff --git a/test/MC/Disassembler/ARM/thumb-tests.txt b/test/MC/Disassembler/ARM/thumb-tests.txt
index 959c8cf7a25c47a5e437e5120e801b323f44ac67..f431bf33af72bddc73fd49e2a0500732e1211eb4 100644 (file)
--- a/test/MC/Disassembler/ARM/thumb-tests.txt
+++ b/test/MC/Disassembler/ARM/thumb-tests.txt
@@ -292,3 +292,6 @@
 
 # CHECK: uxtb16        r9, r12, ror #16
 0x3f 0xfa 0xec 0xf9
+
+# CHECK: pldw  [r11, r12, lsl #2]
+0x3b 0xf8 0x2c 0xf0