UPSTREAM: ARM: DTS: Fix register map for virt-capable GIC
authorMarc Zyngier <marc.zyngier@arm.com>
Wed, 18 Jan 2017 09:27:28 +0000 (09:27 +0000)
committerHuang, Tao <huangtao@rock-chips.com>
Wed, 19 Apr 2017 09:21:35 +0000 (17:21 +0800)
Since everybody copied my own mistake from the DT binding example,
let's address all the offenders in one swift go.

Most of them got the CPU interface size wrong (4kB, while it should
be 8kB), except for both keystone platforms which got the control
interface wrong (4kB instead of 8kB).

In a few cases where I knew for sure what implementation was used,
I've added the "arm,gic-400" compatible string. I'm 99% sure that
this is what everyone is using, but short of having the TRM for
all the other SoCs, I've left them alone.

Change-Id: I15f66453fa9db952d1758cd5b61432405b019dc8
Acked-by: Shawn Guo <shawnguo@kernel.org>
Acked-by: Tony Lindgren <tony@atomide.com>
Acked-by: Santosh Shilimkar <ssantosh@kernel.org>
Acked-by: Krzysztof Kozlowski <krzk@kernel.org>
Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Acked-by: Antoine Tenart <antoine.tenart@free-electrons.com>
Acked-by: Arnd Bergmann <arnd@arndb.de>
Acked-by: Matthias Brugger <matthias.bgg@gmail.com>
Acked-by: Heiko Stuebner <heiko@sntech.de>
Reviewed-by: Javier Martinez Canillas <javier@osg.samsung.com>
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
(cherry picked from commit 387720c93812f1e702c20c667cb003a356e24a6c)
Signed-off-by: Jacob Chen <jacob2.chen@rock-chips.com>
arch/arm/boot/dts/rk3036.dtsi
arch/arm/boot/dts/rk322x.dtsi
arch/arm/boot/dts/rk3288.dtsi

index b62836406e0a359dba1c890ee5e2639b525df413..37d283fef3b202a79a4c340c55fc833bafeab67d 100644 (file)
                #address-cells = <0>;
 
                reg = <0x10139000 0x1000>,
-                     <0x1013a000 0x1000>,
+                     <0x1013a000 0x2000>,
                      <0x1013c000 0x2000>,
                      <0x1013e000 0x2000>;
                interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>;
index 3a97c25a9ca721911536f5d6aa6164d583daabaa..b9d8325388af6373b01b0f15a0d71bd3881ea5c7 100644 (file)
                #address-cells = <0>;
 
                reg = <0x32011000 0x1000>,
-                     <0x32012000 0x1000>,
+                     <0x32012000 0x2000>,
                      <0x32014000 0x2000>,
                      <0x32016000 0x2000>;
                interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
index b8448ec448ee57e499a615c828f4c6e3f356c03f..730e2ed6ad3517737283a74cf27e617c93070e53 100644 (file)
                #address-cells = <0>;
 
                reg = <0xffc01000 0x1000>,
-                     <0xffc02000 0x1000>,
+                     <0xffc02000 0x2000>,
                      <0xffc04000 0x2000>,
                      <0xffc06000 0x2000>;
                interrupts = <GIC_PPI 9 0xf04>;