- Remove scalar to vector pseudo ops. They are just wrong.

- Handle FR32 to VR128:v4f32 and FR64 to VR128:v2f64 with aliases of MOVAPS
and MOVAPD. Mark them as move instructions and *hope* they will be deleted.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26919 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/lib/Target/X86/X86InstrInfo.cpp b/lib/Target/X86/X86InstrInfo.cpp
index 17757726a2d2d82de3f8e51678ce382c9c8a2712..1de163a01eef62b43ae9d9ed83e8636f8115a7cd 100644 (file)
--- a/lib/Target/X86/X86InstrInfo.cpp
+++ b/lib/Target/X86/X86InstrInfo.cpp
@@ -30,7 +30,8 @@ bool X86InstrInfo::isMoveInstr(const MachineInstr& MI,
   if (oc == X86::MOV8rr || oc == X86::MOV16rr || oc == X86::MOV32rr ||
       oc == X86::FpMOV  || oc == X86::MOVSSrr || oc == X86::MOVSDrr ||
       oc == X86::FsMOVAPSrr || oc == X86::FsMOVAPDrr ||
-      oc == X86::MOVAPSrr || oc == X86::MOVAPDrr) {
+      oc == X86::MOVAPSrr || oc == X86::MOVAPDrr ||
+      oc == X86::FR32ToV4F32 || oc == X86::FR64ToV2F64) {
       assert(MI.getNumOperands() == 2 &&
              MI.getOperand(0).isRegister() &&
              MI.getOperand(1).isRegister() &&

diff --git a/lib/Target/X86/X86InstrMMX.td b/lib/Target/X86/X86InstrMMX.td
index 41523402254b3c530bc186eb538d1838e3600e49..244cac69d1f11648b8d2e648a2c9821f62b34562 100644 (file)
--- a/lib/Target/X86/X86InstrMMX.td
+++ b/lib/Target/X86/X86InstrMMX.td
@@ -22,24 +22,6 @@ def IMPLICIT_DEF_VR64 : I<0, Pseudo, (ops VR64:$dst),
 def : Pat<(v4i16 (undef)), (IMPLICIT_DEF_VR64)>,  Requires<[HasMMX]>;
 def : Pat<(v2i32 (undef)), (IMPLICIT_DEF_VR64)>,  Requires<[HasMMX]>;
 
-def SCALAR_TO_VECTOR_V8I8 : I<0, Pseudo, (ops VR64:$dst, R8:$src),
-                              "#SCALAR_TO_VECTOR $src",
-                              [(set VR64:$dst,
-                                (v8i8 (scalar_to_vector R8:$src)))]>,
-                            Requires<[HasMMX]>;
-
-def SCALAR_TO_VECTOR_V4I16 : I<0, Pseudo, (ops VR64:$dst, R16:$src),
-                               "#SCALAR_TO_VECTOR $src",
-                               [(set VR64:$dst,
-                                 (v4i16 (scalar_to_vector R16:$src)))]>,
-                             Requires<[HasMMX]>;
-
-def SCALAR_TO_VECTOR_V2I32 : I<0, Pseudo, (ops VR64:$dst, R32:$src),
-                               "#SCALAR_TO_VECTOR $src",
-                               [(set VR64:$dst,
-                                 (v2i32 (scalar_to_vector R32:$src)))]>,
-                             Requires<[HasMMX]>;
-
 // Move Instructions
 def MOVD64rr : I<0x6E, MRMSrcReg, (ops VR64:$dst, R32:$src),
                  "movd {$src, $dst|$dst, $src}", []>, TB,
@@ -60,4 +42,3 @@ def MOVQ64rm : I<0x6F, MRMSrcMem, (ops VR64:$dst, i64mem:$src),
 def MOVQ64mr : I<0x7F, MRMDestMem, (ops i64mem:$dst, VR64:$src),
                  "movq {$src, $dst|$dst, $src}", []>, TB,
                Requires<[HasMMX]>;
-

diff --git a/lib/Target/X86/X86InstrSSE.td b/lib/Target/X86/X86InstrSSE.td
index f8efb5101eef2ad65eead16ff121a48dbedf96b7..b80b8e08efbad903292f446206e5b179b0e237e0 100644 (file)
--- a/lib/Target/X86/X86InstrSSE.td
+++ b/lib/Target/X86/X86InstrSSE.td
@@ -353,42 +353,6 @@ def : Pat<(v8i16 (undef)), (IMPLICIT_DEF_VR128)>, Requires<[HasSSE2]>;
 def : Pat<(v4i32 (undef)), (IMPLICIT_DEF_VR128)>, Requires<[HasSSE2]>;
 def : Pat<(v2i64 (undef)), (IMPLICIT_DEF_VR128)>, Requires<[HasSSE2]>;
 
-def SCALAR_TO_VECTOR_V4F32 : I<0, Pseudo, (ops VR128:$dst, FR32:$src),
-                               "#SCALAR_TO_VECTOR $src",
-                               [(set VR128:$dst,
-                                 (v4f32 (scalar_to_vector FR32:$src)))]>,
-                             Requires<[HasSSE1]>;
-
-def SCALAR_TO_VECTOR_V2F64 : I<0, Pseudo, (ops VR128:$dst, FR64:$src),
-                               "#SCALAR_TO_VECTOR $src",
-                               [(set VR128:$dst,
-                                 (v2f64 (scalar_to_vector FR64:$src)))]>,
-                             Requires<[HasSSE2]>;
-
-def SCALAR_TO_VECTOR_V16I8 : I<0, Pseudo, (ops VR128:$dst, R8:$src),
-                               "#SCALAR_TO_VECTOR $src",
-                               [(set VR128:$dst,
-                                 (v16i8 (scalar_to_vector R8:$src)))]>,
-                             Requires<[HasSSE2]>;
-
-def SCALAR_TO_VECTOR_V8I16 : I<0, Pseudo, (ops VR128:$dst, R16:$src),
-                               "#SCALAR_TO_VECTOR $src",
-                               [(set VR128:$dst,
-                                 (v8i16 (scalar_to_vector R16:$src)))]>,
-                             Requires<[HasSSE2]>;
-
-def SCALAR_TO_VECTOR_V4I32 : I<0, Pseudo, (ops VR128:$dst, R32:$src),
-                               "#SCALAR_TO_VECTOR $src",
-                               [(set VR128:$dst,
-                                 (v4i32 (scalar_to_vector R32:$src)))]>,
-                             Requires<[HasSSE2]>;
-
-def SCALAR_TO_VECTOR_V2I64 : I<0, Pseudo, (ops VR128:$dst, VR64:$src),
-                               "#SCALAR_TO_VECTOR $src",
-                               [(set VR128:$dst,
-                                 (v2i64 (scalar_to_vector VR64:$src)))]>,
-                             Requires<[HasSSE2]>;
-
 // Move Instructions
 def MOVAPSrr : PSI<0x28, MRMSrcReg, (ops VR128:$dst, VR128:$src),
                    "movaps {$src, $dst|$dst, $src}", []>;
@@ -752,3 +716,18 @@ def MOVQ128rm : I<0x7E, MRMSrcMem, (ops VR128:$dst, i64mem:$src),
 
 def MOVQ128mr : PDI<0xD6, MRMSrcMem, (ops i64mem:$dst, VR128:$src),
                   "movq {$src, $dst|$dst, $src}", []>;
+
+
+//===----------------------------------------------------------------------===//
+// Alias Instructions
+//===----------------------------------------------------------------------===//
+
+def FR32ToV4F32 : PSI<0x28, MRMSrcReg, (ops VR128:$dst, FR32:$src),
+                      "movaps {$src, $dst|$dst, $src}",
+                      [(set VR128:$dst,
+                        (v4f32 (scalar_to_vector FR32:$src)))]>;
+
+def FR64ToV2F64 : PDI<0x28, MRMSrcReg, (ops VR128:$dst, FR64:$src),
+                      "movapd {$src, $dst|$dst, $src}",
+                      [(set VR128:$dst,
+                        (v2f64 (scalar_to_vector FR64:$src)))]>;