*/
#include <dt-bindings/clock/rockchip,rk3368.h>
-
-
/{
clocks {
compatible = "rockchip,rk-clocks";
- #address-cells = <1>;
- #size-cells = <1>;
+ rockchip,grf = <&grf>;
+ #address-cells = <2>;
+ #size-cells = <2>;
ranges;
fixed_rate_cons {
compatible = "rockchip,rk-clock-regs";
#address-cells = <1>;
#size-cells = <1>;
- ranges = <0x0 0xFF760000 0x0264>;
- reg = <0xFF760000 0x0264>;/* NEED CONFIRM */
+ ranges = <0x0 0x0 0xff760000 0x1000>;
+ reg = <0x0 0xff760000 0x0 0x1000>;
/* PLL control regs */
pll_cons {
rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
#clock-cells = <0>;
rockchip,clkops-idx = <CLKOPS_RATE_MUX_DIV>;
+ rockchip,flags = <CLK_SET_RATE_NO_REPARENT>;
};
/* 5 reserved */
compatible = "rockchip,rk3188-div-con";
rockchip,bits = <0 5>;
clocks = <&aclk_bus>;
- clock-output-names = "aclk_bus_div";
+ clock-output-names = "aclk_bus";
rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
#clock-cells = <0>;
rockchip,clkops-idx = <CLKOPS_RATE_MUX_DIV>;
compatible = "rockchip,rk3188-div-con";
rockchip,bits = <0 5>;
clocks = <&aclk_peri>;
- clock-output-names = "aclk_peri_div";
+ clock-output-names = "aclk_peri";
rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
#clock-cells = <0>;
rockchip,clkops-idx = <CLKOPS_RATE_MUX_DIV>;
clock-output-names = "aclk_gpu_cfg";
rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
#clock-cells = <0>;
+ #clock-init-cells = <1>;
};
};
clocks = <&clk_cpll>, <&clk_gpll>, <&clk_npll>, <&clk_npll>;
clock-output-names = "clk_edp";
#clock-cells = <0>;
+ #clock-init-cells = <1>;
};
clk_edp_24m: clk_edp_24m_mux {
clocks = <&clk_cpll>, <&clk_gpll>;
clock-output-names = "clk_uart_pll";
#clock-cells = <0>;
+ #clock-init-cells = <1>;
};
/* 14:13 reserved */
rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
#clock-cells = <0>;
rockchip,clkops-idx = <CLKOPS_RATE_MUX_DIV>;
+ rockchip,flags = <CLK_SET_RATE_NO_REPARENT>;
};
/* 7 reserved */
<&aclk_gpu_mem>, <&aclk_gpu_cfg>,
<&dummy>, <&dummy>,
- <&dummy>, <&i2s_pll>,
+ <&dummy>, <&i2s_2ch_pll>,
<&i2s_2ch_frac>, <&clk_i2s_2ch>;
clock-output-names =
"aclk_gpu_mem", "aclk_gpu_cfg",
"reserved", "reserved",
- "reserved", "i2s_pll",
+ "reserved", "i2s_2ch_pll",
"i2s_2ch_frac", "clk_i2s_2ch";
#clock-cells = <1>;
"g_aclk_iep", "g_hclk_iep",
"g_aclk_vop_iep", "g_aclk_vop",
- "g_hclk_vop", "g_h_vio_ahb_arbi",
+ "g_hclk_vop", "h_vio_ahb_arbi",
"g_hclk_vio_noc", "g_aclk_vio0_noc",
"g_aclk_vio1_noc", "g_aclk_vip",
<&pclk_peri>, <&pclk_peri>;
clock-output-names =
- "g_h_p_axi_matrix", "g_p_p_axi_matrix",
- "g_a_p_axi_matrix", "g_a_dmac_peri",
+ "g_hp_axi_matrix", "g_pp_axi_matrix",
+ "g_ap_axi_matrix", "g_a_dmac_peri",
"g_pclk_spi0", "g_pclk_spi1",
"g_pclk_spi2", "g_pclk_uart0",
special_regs {
compatible = "rockchip,rk-clock-special-regs";
- #address-cells = <1>;
- #size-cells = <1>;
+ #address-cells = <2>;
+ #size-cells = <2>;
ranges;
clk_32k_mux: clk_32k_mux {
compatible = "rockchip,rk3188-mux-con";
- reg = <0xff738100 0x4>;
+ reg = <0x0 0xff738100 0x0 0x4>;
rockchip,bits = <6 1>;
clocks = <&xin32k>, <&clk_gates7 3>;
clock-output-names = "clk_32k_mux";
#include <dt-bindings/pinctrl/rockchip.h>
#include <dt-bindings/pinctrl/rockchip-rk3288.h>
-#include "skeleton.dtsi"
#include "rk3368-clocks.dtsi"
/ {
rockchip,clocks-init-parent =
<&i2s_pll &clk_gpll>, <&spdif_8ch_pll &clk_gpll>,
<&i2s_2ch_pll &clk_gpll>, <&usbphy_480m &usbotg_480m_out>,
- <&clk_uart_pll &clk_gpll>, <&aclk_gpu &clk_cpll>;
+ <&clk_uart_pll &clk_gpll>, <&aclk_gpu &clk_cpll>,
+ <&clk_cs &clk_gpll>;
rockchip,clocks-init-rate =
<&clk_core_b 792000000>, <&clk_core_l 600000000>,
<&clk_gpll 576000000>, <&clk_cpll 400000000>,
<&clk_crypto 150000000>, <&aclk_peri 300000000>,
<&hclk_peri 150000000>, <&pclk_peri 75000000>,
<&pclk_alive_pre 100000000>, <&pclk_pmu_pre 100000000>,
+ <&clk_cs 300000000>, <&clkin_trace 300000000>,
+ <&aclk_cci 600000000>, <&clk_mac 50000000>,
<&aclk_vio0 400000000>, <&hclk_vio 100000000>,
<&aclk_rga_pre 400000000>, <&clk_rga 400000000>,
<&clk_isp 400000000>, <&clk_edp 200000000>,
<&clk_gpu_core 400000000>, <&aclk_gpu_mem 400000000>,
<&aclk_gpu_cfg 400000000>, <&aclk_vepu 400000000>,
<&aclk_vdpu 400000000>, <&clk_hevc_core 300000000>,
- <&clk_hevc_cabac 300000000>, <&clk_mac 50000000>;
+ <&clk_hevc_cabac 300000000>;
/*rockchip,clocks-uboot-has-init =
<&aclk_vio0>;*/
};
.set_rate = NULL,
};
+#if 0
static unsigned long clk_ddr_recalc_rate(struct clk_hw *hw,
unsigned long parent_rate)
{
.set_rate = clk_ddr_set_rate,
.determine_rate = clk_ddr_determine_rate,
};
+#endif
static unsigned long clk_3288_i2s_recalc_rate(struct clk_hw *hw,
unsigned long parent_rate)
{.index = CLKOPS_RATE_FRAC, .clk_ops = &clkops_rate_frac},
{.index = CLKOPS_RATE_CORE, .clk_ops = &clkops_rate_core},
{.index = CLKOPS_RATE_CORE_CHILD, .clk_ops = &clkops_rate_core_peri},
- {.index = CLKOPS_RATE_DDR, .clk_ops = &clkops_rate_ddr},
+ {.index = CLKOPS_RATE_DDR, .clk_ops = NULL},
{.index = CLKOPS_RATE_RK3288_I2S, .clk_ops = &clkops_rate_3288_i2s},
{.index = CLKOPS_RATE_RK3288_USB480M, .clk_ops = &clkops_rate_3288_usb480m},
{.index = CLKOPS_RATE_RK3288_DCLK_LCDC0,.clk_ops = &clkops_rate_3288_dclk_lcdc0},
{.index = CLKOPS_RATE_RK3288_DCLK_LCDC1,.clk_ops = &clkops_rate_3288_dclk_lcdc1},
- {.index = CLKOPS_RATE_DDR_DIV2, .clk_ops = &clkops_rate_ddr_div2},
- {.index = CLKOPS_RATE_DDR_DIV4, .clk_ops = &clkops_rate_ddr_div4},
+ {.index = CLKOPS_RATE_DDR_DIV2, .clk_ops = NULL},
+ {.index = CLKOPS_RATE_DDR_DIV4, .clk_ops = NULL},
{.index = CLKOPS_RATE_RK3368_MUX_DIV_NPLL, .clk_ops = &clkops_rate_3368_auto_parent},
{.index = CLKOPS_RATE_I2S, .clk_ops = NULL},
{.index = CLKOPS_RATE_CIFOUT, .clk_ops = NULL},
#define clk_err(fmt, args...) printk(KERN_ERR "rkclk: "fmt, ##args)
+u32 cru_readl(u32 offset);
+void cru_writel(u32 val, u32 offset);
-#define cru_readl(offset) readl(RK_CRU_VIRT + (offset))
-#define cru_writel(v, o) do {writel(v, RK_CRU_VIRT + (o)); dsb();} \
- while (0)
-#define grf_readl(offset) readl_relaxed(RK_GRF_VIRT + (offset))
+u32 grf_readl(u32 offset);
#endif /* __RK_CLKOPS_H */
{
struct clk_pd *pd = to_clk_pd(hw);
unsigned long flags = 0;
- int ret;
+ int ret = 0;
if (pd->lock)
spin_lock_irqsave(pd->lock, flags);
- ret = rockchip_pmu_ops.set_power_domain(pd->id, enable);
+ /* ret = rockchip_pmu_ops.set_power_domain(pd->id, enable); */
if (pd->lock)
spin_unlock_irqrestore(pd->lock, flags);
__clk_pd_notify(hw->clk, RK_CLK_PD_POST_DISABLE);
}
+/*
static int clk_pd_is_enabled(struct clk_hw *hw)
{
struct clk_pd *pd = to_clk_pd(hw);
return rockchip_pmu_ops.power_domain_is_on(pd->id);
}
+*/
static int clk_pd_prepare(struct clk_hw *hw)
{
.unprepare = clk_pd_unprepare,
.enable = clk_pd_enable,
.disable = clk_pd_disable,
- .is_enabled = clk_pd_is_enabled,
+ /*.is_enabled = clk_pd_is_enabled,*/
};
static int clk_pd_virt_enable(struct clk_hw *hw)
struct clk_pll *pll = to_clk_pll(hw);
int delay = 24000000;
-
while (delay > 0) {
if (grf_readl(pll->status_offset) & (1 << pll->status_shift))
break;
/* reparent to apll, and set div to 1 */
if (sel_gpll) {
if (temp_div == 1) {
- /* when rate/2 < (old_rate-arm_gpll_rate),
+ /* when rate/2 < (rate-arm_gpll_rate),
we can set div to make rate change more gently */
if (rate > (2*arm_gpll_rate)) {
cru_writel(RK3288_CORE_CLK_DIV(2), RK3288_CRU_CLKSELS_CON(0));
unsigned long flags;
int sel_gpll = 0;
+ ps = apll_get_best_set(rate, rk3368_apllb_table);
+ clk_debug("apllb will set rate %lu\n", ps->rate);
+ clk_debug("table con:%08x,%08x,%08x, sel:%08x,%08x\n",
+ ps->pllcon0, ps->pllcon1, ps->pllcon2,
+ ps->clksel0, ps->clksel1);
#if !RK3368_APLLB_USE_GPLL
goto CHANGE_APLL;
local_irq_save(flags);
+ if (rate >= old_rate) {
+ cru_writel(ps->clksel0, RK3368_CRU_CLKSELS_CON(0));
+ cru_writel(ps->clksel1, RK3368_CRU_CLKSELS_CON(1));
+ }
+
/* select gpll */
#if RK3368_APLLB_DIV_MORE
if (temp_div == 1) {
temp_div);
CHANGE_APLL:
- ps = apll_get_best_set(rate, rk3368_apllb_table);
- clk_debug("apll will set rate %lu\n", ps->rate);
- clk_debug("table con:%08x,%08x,%08x, sel:%08x,%08x\n",
- ps->pllcon0, ps->pllcon1, ps->pllcon2,
- ps->clksel0, ps->clksel1);
-
local_irq_save(flags);
/* If core src don't select gpll, apll need to enter slow mode
udelay(ps->rst_dly);
pll_wait_lock(hw);
- if (rate >= __clk_get_rate(hw->clk)) {
- cru_writel(ps->clksel0, RK3368_CRU_CLKSELS_CON(0));
- cru_writel(ps->clksel1, RK3368_CRU_CLKSELS_CON(1));
- }
-
/* PLL return from slow mode */
- if (!sel_gpll)
+ if (!sel_gpll) {
+ if (rate >= old_rate) {
+ cru_writel(ps->clksel0, RK3368_CRU_CLKSELS_CON(0));
+ cru_writel(ps->clksel1, RK3368_CRU_CLKSELS_CON(1));
+ }
cru_writel(_RK3188_PLL_MODE_NORM_SET(pll->mode_shift),
pll->mode_offset);
+ }
/* reparent to apll, and set div to 1 */
if (sel_gpll) {
#if RK3368_APLLB_DIV_MORE
if (temp_div == 1) {
- /* when rate/2 < (old_rate-arm_gpll_rate),
+ /* when rate/2 < (rate-arm_gpll_rate),
we can set div to make rate change more gently */
if (rate > (2*arm_gpll_rate)) {
cru_writel(RK3368_CORE_CLK_DIV(2), RK3368_CRU_CLKSELS_CON(0));
#endif
}
- if (rate < __clk_get_rate(hw->clk)) {
+ if (rate < old_rate) {
cru_writel(ps->clksel0, RK3368_CRU_CLKSELS_CON(0));
cru_writel(ps->clksel1, RK3368_CRU_CLKSELS_CON(1));
}
unsigned long flags;
int sel_gpll = 0;
+ ps = apll_get_best_set(rate, rk3368_aplll_table);
+ clk_debug("aplll will set rate %lu\n", ps->rate);
+ clk_debug("table con:%08x,%08x,%08x, sel:%08x,%08x\n",
+ ps->pllcon0, ps->pllcon1, ps->pllcon2,
+ ps->clksel0, ps->clksel1);
#if !RK3368_APLLL_USE_GPLL
goto CHANGE_APLL;
local_irq_save(flags);
+ if (rate >= old_rate) {
+ cru_writel(ps->clksel0, RK3368_CRU_CLKSELS_CON(2));
+ cru_writel(ps->clksel1, RK3368_CRU_CLKSELS_CON(3));
+ }
+
/* select gpll */
#if RK3368_APLLL_DIV_MORE
if (temp_div == 1) {
temp_div);
CHANGE_APLL:
- ps = apll_get_best_set(rate, rk3368_aplll_table);
- clk_debug("apll will set rate %lu\n", ps->rate);
- clk_debug("table con:%08x,%08x,%08x, sel:%08x,%08x\n",
- ps->pllcon0, ps->pllcon1, ps->pllcon2,
- ps->clksel0, ps->clksel1);
-
local_irq_save(flags);
/* If core src don't select gpll, apll need to enter slow mode
udelay(ps->rst_dly);
pll_wait_lock(hw);
- if (rate >= __clk_get_rate(hw->clk)) {
- cru_writel(ps->clksel0, RK3368_CRU_CLKSELS_CON(2));
- cru_writel(ps->clksel1, RK3368_CRU_CLKSELS_CON(3));
- }
-
/* PLL return from slow mode */
- if (!sel_gpll)
+ if (!sel_gpll) {
+ if (rate >= old_rate) {
+ cru_writel(ps->clksel0, RK3368_CRU_CLKSELS_CON(2));
+ cru_writel(ps->clksel1, RK3368_CRU_CLKSELS_CON(3));
+ }
cru_writel(_RK3188_PLL_MODE_NORM_SET(pll->mode_shift),
pll->mode_offset);
+ }
/* reparent to apll, and set div to 1 */
if (sel_gpll) {
#if RK3368_APLLL_DIV_MORE
if (temp_div == 1) {
- /* when rate/2 < (old_rate-arm_gpll_rate),
+ /* when rate/2 < (rate-arm_gpll_rate),
we can set div to make rate change more gently */
if (rate > (2*arm_gpll_rate)) {
cru_writel(RK3368_CORE_CLK_DIV(2), RK3368_CRU_CLKSELS_CON(2));
#endif
}
- if (rate < __clk_get_rate(hw->clk)) {
+ if (rate < old_rate) {
cru_writel(ps->clksel0, RK3368_CRU_CLKSELS_CON(2));
cru_writel(ps->clksel1, RK3368_CRU_CLKSELS_CON(3));
}
#include "clk-pll.h"
#include "clk-pd.h"
+static void __iomem *rk_cru_base;
+static void __iomem *rk_grf_base;
+
+u32 cru_readl(u32 offset)
+{
+ return readl(rk_cru_base + (offset));
+}
+
+void cru_writel(u32 val, u32 offset)
+{
+ writel(val, rk_cru_base + (offset));
+ dsb();
+}
+
+u32 grf_readl(u32 offset)
+{
+ return readl(rk_grf_base + (offset));
+}
struct rkclk_muxinfo {
const char *clk_name;
for_each_available_child_of_node(node, node_prd) {
_rkclk_add_provider(node_prd);
}
+ } else if (strcmp(compatible, "rockchip,rk-clock-special-regs") == 0) {
+ for_each_available_child_of_node(node, node_prd) {
+ _rkclk_add_provider(node_prd);
+ }
} else {
clk_err("%s: unknown\n", __func__);
}
void rk_dump_cru(void)
{
printk(KERN_WARNING "CRU:\n");
- print_hex_dump(KERN_WARNING, "", DUMP_PREFIX_OFFSET, 16, 4, RK_CRU_VIRT, 0x220, false);
+ print_hex_dump(KERN_WARNING, "", DUMP_PREFIX_OFFSET, 16, 4, rk_cru_base,
+ 0x220, false);
}
EXPORT_SYMBOL_GPL(rk_dump_cru);
struct rkclk *rkclk;
const char *compatible;
- printk("%s start! cru base = %p\n", __func__, RK_CRU_VIRT);
+ printk("%s start!\n", __func__);
- node_init=of_find_node_by_name(NULL,"clocks-init");
+ node_init = of_find_node_by_name(NULL, "clocks-init");
if (!node_init) {
clk_err("%s: can not get clocks-init node\n", __func__);
return;
}
- clk_root_node=of_find_node_by_name(NULL,"clock_regs");
+ clk_root_node = of_find_node_by_name(NULL, "clock_regs");
+ rk_cru_base = of_iomap(clk_root_node, 0);
+ if (!rk_cru_base) {
+ clk_err("%s: could not map cru region\n", __func__);
+ return;
+ }
+
+ node = of_parse_phandle(np, "rockchip,grf", 0);
+ rk_grf_base = of_iomap(node, 0);
for_each_available_child_of_node(np, node) {
clk_debug("\n");
projects / firefly-linux-kernel-4.4.55.git / commitdiff