MachineBasicBlock *
X86TargetLowering::EmitMonitor(MachineInstr *MI, MachineBasicBlock *BB) const {
- assert((Subtarget->hasSSE3()) && "Target must have SSE3 features enabled");
+ assert(Subtarget->hasSSE3() && "Target must have SSE3 features enabled");
DebugLoc dl = MI->getDebugLoc();
const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
unsigned MemReg = Subtarget->is64Bit() ? X86::RAX : X86::EAX;
MachineInstrBuilder MIB = BuildMI(*BB, MI, dl, TII->get(MemOpc), MemReg);
for (int i = 0; i < X86::AddrNumOperands; ++i)
- (*MIB).addOperand(MI->getOperand(i));
+ MIB.addOperand(MI->getOperand(i));
unsigned ValOps = X86::AddrNumOperands;
BuildMI(*BB, MI, dl, TII->get(TargetOpcode::COPY), X86::ECX)
MachineBasicBlock *
X86TargetLowering::EmitMwait(MachineInstr *MI, MachineBasicBlock *BB) const {
- assert((Subtarget->hasSSE3()) && "Target must have SSE3 features enabled");
+ assert(Subtarget->hasSSE3() && "Target must have SSE3 features enabled");
DebugLoc dl = MI->getDebugLoc();
const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
/// Utility functions to emit monitor and mwait instructions. These
/// need to make sure that the arguments to the intrinsic are in the
/// correct registers.
- MachineBasicBlock *EmitMonitor(MachineInstr *MI, MachineBasicBlock *BB)
- const;
+ MachineBasicBlock *EmitMonitor(MachineInstr *MI,
+ MachineBasicBlock *BB) const;
MachineBasicBlock *EmitMwait(MachineInstr *MI, MachineBasicBlock *BB) const;
/// Utility function to emit atomic bitwise operations (and, or, xor).