As requested, a blurb on sub-targets.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23769 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/docs/CodeGenerator.html b/docs/CodeGenerator.html
index 39eecc1289871a73f01b8ed7205eb92dc6c69b13..0e63faca3cca82f018be2897812e114127fe78e1 100644 (file)
--- a/docs/CodeGenerator.html
+++ b/docs/CodeGenerator.html
@@ -444,7 +444,11 @@ href="TableGenFundamentals.html">TableGen</a> description of the register file.
 
 <div class="doc_text">
   <p>
-  TODO
+  <p>The <tt>TargetSubtarget</tt> class is used to provide information about the
+  specific chip set being targeted.  A sub-target informs code generation of 
+  which instructions are supported, instruction latencies and instruction 
+  execution itinerary; i.e., which processing units are used, in what order, and
+  for how long.
   </p>
 </div>