Merge branch 'x86/apic' into x86/platform

Merge in x86/apic to solve a vector_allocation_domain() API change semantic merge conflict.

Signed-off-by: Ingo Molnar <mingo@kernel.org>

diff --git a/arch/x86/include/asm/x86_init.h b/arch/x86/include/asm/x86_init.h
index 42d2ae18dab2b9f0195380e0c2a675fc3c18c746..38155f667144ce365f83cd13572d98f78bff5446 100644 (file)
--- a/arch/x86/include/asm/x86_init.h
+++ b/arch/x86/include/asm/x86_init.h
@@ -163,6 +163,7 @@ struct x86_cpuinit_ops {
  * @i8042_detect               pre-detect if i8042 controller exists
  * @save_sched_clock_state:    save state for sched_clock() on suspend
  * @restore_sched_clock_state: restore state for sched_clock() on resume
+ * @apic_post_init:            adjust apic if neeeded
  */
 struct x86_platform_ops {
        unsigned long (*calibrate_tsc)(void);
@@ -175,6 +176,7 @@ struct x86_platform_ops {
        int (*i8042_detect)(void);
        void (*save_sched_clock_state)(void);
        void (*restore_sched_clock_state)(void);
+       void (*apic_post_init)(void);
 };
 
 struct pci_dev;

diff --git a/arch/x86/kernel/apic/probe_32.c b/arch/x86/kernel/apic/probe_32.c
index eef6bcd1bf1e8d63abcaea54b3ebdcfc07187e48..eb35ef9ee63f779bde870822a01dcc98bd503b01 100644 (file)
--- a/arch/x86/kernel/apic/probe_32.c
+++ b/arch/x86/kernel/apic/probe_32.c
@@ -192,6 +192,9 @@ void __init default_setup_apic_routing(void)
 
        if (apic->setup_apic_routing)
                apic->setup_apic_routing();
+
+       if (x86_platform.apic_post_init)
+               x86_platform.apic_post_init();
 }
 
 void __init generic_apic_probe(void)

diff --git a/arch/x86/kernel/apic/probe_64.c b/arch/x86/kernel/apic/probe_64.c
index 3fe98669892905c48d3b8eea6ee11bda7100e75d..1793dba7a741bcf22271b71848fa92293bddde70 100644 (file)
--- a/arch/x86/kernel/apic/probe_64.c
+++ b/arch/x86/kernel/apic/probe_64.c
@@ -23,11 +23,6 @@
 #include <asm/ipi.h>
 #include <asm/setup.h>
 
-static int apicid_phys_pkg_id(int initial_apic_id, int index_msb)
-{
-       return hard_smp_processor_id() >> index_msb;
-}
-
 /*
  * Check the APIC IDs in bios_cpu_apicid and choose the APIC mode.
  */
@@ -48,10 +43,8 @@ void __init default_setup_apic_routing(void)
                }
        }
 
-       if (is_vsmp_box()) {
-               /* need to update phys_pkg_id */
-               apic->phys_pkg_id = apicid_phys_pkg_id;
-       }
+       if (x86_platform.apic_post_init)
+               x86_platform.apic_post_init();
 }
 
 /* Same for both flat and physical. */

diff --git a/arch/x86/kernel/vsmp_64.c b/arch/x86/kernel/vsmp_64.c
index 8eeb55a551b423fdce43eb432c8f8f5599246848..3f0285ac00fa6536a19e9a6817fdcbc92c52c4ae 100644 (file)
--- a/arch/x86/kernel/vsmp_64.c
+++ b/arch/x86/kernel/vsmp_64.c
@@ -16,6 +16,7 @@
 #include <linux/pci_ids.h>
 #include <linux/pci_regs.h>
 #include <linux/smp.h>
+#include <linux/irq.h>
 
 #include <asm/apic.h>
 #include <asm/pci-direct.h>
@@ -95,6 +96,18 @@ static void __init set_vsmp_pv_ops(void)
        ctl = readl(address + 4);
        printk(KERN_INFO "vSMP CTL: capabilities:0x%08x  control:0x%08x\n",
               cap, ctl);
+
+       /* If possible, let the vSMP foundation route the interrupt optimally */
+#ifdef CONFIG_SMP
+       if (cap & ctl & BIT(8)) {
+               ctl &= ~BIT(8);
+#ifdef CONFIG_PROC_FS
+               /* Don't let users change irq affinity via procfs */
+               no_irq_affinity = 1;
+#endif
+       }
+#endif
+
        if (cap & ctl & (1 << 4)) {
                /* Setup irq ops and turn on vSMP  IRQ fastpath handling */
                pv_irq_ops.irq_disable = PV_CALLEE_SAVE(vsmp_irq_disable);
@@ -102,12 +115,11 @@ static void __init set_vsmp_pv_ops(void)
                pv_irq_ops.save_fl  = PV_CALLEE_SAVE(vsmp_save_fl);
                pv_irq_ops.restore_fl  = PV_CALLEE_SAVE(vsmp_restore_fl);
                pv_init_ops.patch = vsmp_patch;
-
                ctl &= ~(1 << 4);
-               writel(ctl, address + 4);
-               ctl = readl(address + 4);
-               printk(KERN_INFO "vSMP CTL: control set to:0x%08x\n", ctl);
        }
+       writel(ctl, address + 4);
+       ctl = readl(address + 4);
+       pr_info("vSMP CTL: control set to:0x%08x\n", ctl);
 
        early_iounmap(address, 8);
 }
@@ -187,12 +199,35 @@ static void __init vsmp_cap_cpus(void)
 #endif
 }
 
+static int apicid_phys_pkg_id(int initial_apic_id, int index_msb)
+{
+       return hard_smp_processor_id() >> index_msb;
+}
+
+/*
+ * In vSMP, all cpus should be capable of handling interrupts, regardless of
+ * the APIC used.
+ */
+static void fill_vector_allocation_domain(int cpu, struct cpumask *retmask)
+{
+       cpumask_setall(retmask);
+}
+
+static void vsmp_apic_post_init(void)
+{
+       /* need to update phys_pkg_id */
+       apic->phys_pkg_id = apicid_phys_pkg_id;
+       apic->vector_allocation_domain = fill_vector_allocation_domain;
+}
+
 void __init vsmp_init(void)
 {
        detect_vsmp_box();
        if (!is_vsmp_box())
                return;
 
+       x86_platform.apic_post_init = vsmp_apic_post_init;
+
        vsmp_cap_cpus();
 
        set_vsmp_pv_ops();