Add a subtarget feature 'v8' to the ARM backend.

This allows for targeting the ARMv8 AArch32 variant.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184967 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/lib/Target/ARM/ARM.td b/lib/Target/ARM/ARM.td
index 1bc9d6b410d54249c680d37a0a90cda6f4bb4797..134b83c2b56a49a93169e7b6288c7c20220c9ac5 100644 (file)
--- a/lib/Target/ARM/ARM.td
+++ b/lib/Target/ARM/ARM.td
@@ -138,6 +138,9 @@ def HasV6T2Ops  : SubtargetFeature<"v6t2", "HasV6T2Ops", "true",
 def HasV7Ops    : SubtargetFeature<"v7", "HasV7Ops", "true",
                                    "Support ARM v7 instructions",
                                    [HasV6T2Ops, FeaturePerfMon]>;
+def HasV8Ops    : SubtargetFeature<"v8", "HasV8Ops", "true",
+                                   "Support ARM v8 instructions",
+                                   [HasV7Ops]>;
 
 //===----------------------------------------------------------------------===//
 // ARM Processors supported.
@@ -291,6 +294,9 @@ def : ProcessorModel<"swift",       SwiftModel,
                                      FeatureDB, FeatureDSPThumb2,
                                      FeatureHasRAS]>;
 
+// V8 Processors
+def : ProcNoItin<"cortex-a53",      [HasV8Ops]>;
+
 //===----------------------------------------------------------------------===//
 // Register File Description
 //===----------------------------------------------------------------------===//

diff --git a/lib/Target/ARM/ARMAsmPrinter.cpp b/lib/Target/ARM/ARMAsmPrinter.cpp
index f8d4da58f0b82418a0b5d281a8f394a08265b2d2..d5b2cf51847e55e8f3d29d457723bf1a83120c45 100644 (file)
--- a/lib/Target/ARM/ARMAsmPrinter.cpp
+++ b/lib/Target/ARM/ARMAsmPrinter.cpp
@@ -749,7 +749,9 @@ void ARMAsmPrinter::emitAttributes() {
                                ARMBuildAttrs::Allowed);
     AttrEmitter->EmitAttribute(ARMBuildAttrs::THUMB_ISA_use,
                                ARMBuildAttrs::Allowed);
-  } else if (Subtarget->hasV7Ops()) {
+  } else if (Subtarget->hasV8Ops())
+    AttrEmitter->EmitAttribute(ARMBuildAttrs::CPU_arch, ARMBuildAttrs::v8);
+  else if (Subtarget->hasV7Ops()) {
     AttrEmitter->EmitAttribute(ARMBuildAttrs::CPU_arch, ARMBuildAttrs::v7);
     AttrEmitter->EmitAttribute(ARMBuildAttrs::THUMB_ISA_use,
                                ARMBuildAttrs::AllowThumb32);

diff --git a/lib/Target/ARM/ARMBuildAttrs.h b/lib/Target/ARM/ARMBuildAttrs.h
index 11bd6a4a8dbc6c94c3930cb9d1067373416b2d46..3dfa7e708c4a135391c964a495c58ff9b37790cf 100644 (file)
--- a/lib/Target/ARM/ARMBuildAttrs.h
+++ b/lib/Target/ARM/ARMBuildAttrs.h
@@ -89,7 +89,8 @@ namespace ARMBuildAttrs {
     v7       = 10,  // e.g. Cortex A8, Cortex M3
     v6_M     = 11,  // e.g. Cortex M1
     v6S_M    = 12,  // v6_M with the System extensions
-    v7E_M    = 13   // v7_M with DSP extensions
+    v7E_M    = 13,  // v7_M with DSP extensions
+    v8       = 14   // v8, AArch32
   };
 
   enum CPUArchProfile { // (=7), uleb128 

diff --git a/lib/Target/ARM/ARMInstrInfo.td b/lib/Target/ARM/ARMInstrInfo.td
index 7f32c1f014c48ef3d2537d9e9c82bd2adaa3f308..ae874426bcb88dbaff9800176fc0ce4b5aa7ba6b 100644 (file)
--- a/lib/Target/ARM/ARMInstrInfo.td
+++ b/lib/Target/ARM/ARMInstrInfo.td
@@ -194,6 +194,8 @@ def HasV6T2          : Predicate<"Subtarget->hasV6T2Ops()">,
 def NoV6T2           : Predicate<"!Subtarget->hasV6T2Ops()">;
 def HasV7            : Predicate<"Subtarget->hasV7Ops()">,
                                  AssemblerPredicate<"HasV7Ops", "armv7">;
+def HasV8            : Predicate<"Subtarget->hasV8Ops()">,
+                                 AssemblerPredicate<"HasV8Ops", "armv8">;
 def NoVFP            : Predicate<"!Subtarget->hasVFP2()">;
 def HasVFP2          : Predicate<"Subtarget->hasVFP2()">,
                                  AssemblerPredicate<"FeatureVFP2", "VFP2">;

diff --git a/lib/Target/ARM/ARMSubtarget.cpp b/lib/Target/ARM/ARMSubtarget.cpp
index 455fe1abe9ace492cbc80095b8803db06aa3d34e..3a5d4bb8ab4209e0fe6852070ea95327c4273f6b 100644 (file)
--- a/lib/Target/ARM/ARMSubtarget.cpp
+++ b/lib/Target/ARM/ARMSubtarget.cpp
@@ -77,6 +77,7 @@ void ARMSubtarget::initializeEnvironment() {
   HasV6Ops = false;
   HasV6T2Ops = false;
   HasV7Ops = false;
+  HasV8Ops = false;
   HasVFPv2 = false;
   HasVFPv3 = false;
   HasVFPv4 = false;

diff --git a/lib/Target/ARM/ARMSubtarget.h b/lib/Target/ARM/ARMSubtarget.h
index bc5af96c606381913ee84bdbcfc07bf2d1b9a481..ad9c0d042e0a29e69420a9385c20ec4b46d1d1a8 100644 (file)
--- a/lib/Target/ARM/ARMSubtarget.h
+++ b/lib/Target/ARM/ARMSubtarget.h
@@ -37,7 +37,8 @@ protected:
   /// ARMProcFamily - ARM processor family: Cortex-A8, Cortex-A9, and others.
   ARMProcFamilyEnum ARMProcFamily;
 
-  /// HasV4TOps, HasV5TOps, HasV5TEOps, HasV6Ops, HasV6T2Ops, HasV7Ops -
+  /// HasV4TOps, HasV5TOps, HasV5TEOps,
+  /// HasV6Ops, HasV6T2Ops, HasV7Ops, HasV8Ops -
   /// Specify whether target support specific ARM ISA variants.
   bool HasV4TOps;
   bool HasV5TOps;
@@ -45,6 +46,7 @@ protected:
   bool HasV6Ops;
   bool HasV6T2Ops;
   bool HasV7Ops;
+  bool HasV8Ops;
 
   /// HasVFPv2, HasVFPv3, HasVFPv4, HasNEON - Specify what
   /// floating point ISAs are supported.
@@ -231,6 +233,7 @@ public:
   bool hasV6Ops()   const { return HasV6Ops;   }
   bool hasV6T2Ops() const { return HasV6T2Ops; }
   bool hasV7Ops()   const { return HasV7Ops;  }
+  bool hasV8Ops()   const { return HasV8Ops;  }
 
   bool isCortexA5() const { return ARMProcFamily == CortexA5; }
   bool isCortexA8() const { return ARMProcFamily == CortexA8; }

diff --git a/lib/Target/ARM/AsmParser/ARMAsmParser.cpp b/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
index eda55502d2dcd547328d6abcc4d302a041a48965..ba2bf8eeca99bb1f7af8328ebfb06e4990fff471 100644 (file)
--- a/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
+++ b/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
@@ -161,6 +161,9 @@ class ARMAsmParser : public MCTargetAsmParser {
   bool hasV7Ops() const {
     return STI.getFeatureBits() & ARM::HasV7Ops;
   }
+  bool hasV8Ops() const {
+    return STI.getFeatureBits() & ARM::HasV8Ops;
+  }
   bool hasARM() const {
     return !(STI.getFeatureBits() & ARM::FeatureNoARM);
   }

diff --git a/lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.cpp b/lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.cpp
index 14fd03fad8eaaa0a1fabb87f4025510171cd6aab..caa19495bbf37dabd52c54fe8019562e43986e50 100644 (file)
--- a/lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.cpp
+++ b/lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.cpp
@@ -59,7 +59,10 @@ std::string ARM_MC::ParseARMTriple(StringRef TT, StringRef CPU) {
   std::string ARMArchFeature;
   if (Idx) {
     unsigned SubVer = TT[Idx];
-    if (SubVer >= '7' && SubVer <= '9') {
+    if (SubVer == '8') {
+      // FIXME: Parse v8 features
+      ARMArchFeature = "+v8";
+    } else if (SubVer == '7') {
       if (Len >= Idx+2 && TT[Idx+1] == 'm') {
         isThumb = true;
         if (NoCPU)

diff --git a/test/CodeGen/ARM/2010-09-29-mc-asm-header-test.ll b/test/CodeGen/ARM/2010-09-29-mc-asm-header-test.ll
index bda14bcb15202e638ea91b524d0cfcfa485a834e..e9cd3f224fe647b8c8a5d1a2e89f253528e61f03 100644 (file)
--- a/test/CodeGen/ARM/2010-09-29-mc-asm-header-test.ll
+++ b/test/CodeGen/ARM/2010-09-29-mc-asm-header-test.ll
@@ -1,12 +1,21 @@
-; RUN: llc < %s -mtriple=arm-linux-gnueabi | FileCheck %s
+; RUN: llc < %s -mtriple=armv7-linux-gnueabi | FileCheck %s --check-prefix=V7
+; RUN: llc < %s -mtriple=armv8-linux-gnueabi | FileCheck %s --check-prefix=V8
+; RUN: llc < %s -mtriple=thumbv8-linux-gnueabi | FileCheck %s --check-prefix=Vt8
 ; This tests that MC/asm header conversion is smooth
 ;
-; CHECK:      .syntax unified
-; CHECK: .eabi_attribute 20, 1
-; CHECK: .eabi_attribute 21, 1
-; CHECK: .eabi_attribute 23, 3
-; CHECK: .eabi_attribute 24, 1
-; CHECK: .eabi_attribute 25, 1
+; V7:      .syntax unified
+; V7: .eabi_attribute 6, 10
+; V7: .eabi_attribute 20, 1
+; V7: .eabi_attribute 21, 1
+; V7: .eabi_attribute 23, 3
+; V7: .eabi_attribute 24, 1
+; V7: .eabi_attribute 25, 1
+
+; V8:      .syntax unified
+; V8: .eabi_attribute 6, 14
+
+; Vt8:     .syntax unified
+; Vt8: .eabi_attribute 6, 14
 
 define i32 @f(i64 %z) {
        ret i32 0