lvds: lvds@ff968000 {
compatible = "rockchip,rk3368-lvds";
+ rockchip,grf = <&grf>;
reg = <0x0 0xff968000 0x0 0x4000>, <0x0 0xff9600b0 0x0 0x01>;
reg-names = "mipi_lvds_phy", "mipi_lvds_ctl";
clocks = <&clk_gates22 10>, <&clk_gates17 3>;
#define grf_writel(v,offset) \
do { \
writel_relaxed(v, RK_GRF_VIRT + offset); \
- dsb(); \
+ dsb(sy); \
} while (0)
val |= v_RK3368_MIPIPHY_LANE0_EN(1) |
v_RK3368_MIPIDPI_FORCEX_EN(1);
/*rk3368 RK3368_GRF_SOC_CON7 = 0X0041C*/
- grf_writel(val, 0x0041C);
+ /*grf_writel(val, 0x0041C);*/
+ regmap_write(lvds->grf_lvds_base, GRF_SOC_CON7_LVDS, val);
+ dsb(sy);
} else {
/* enable lvds mode */
val |= v_LVDSMODE_EN(1) | v_MIPIPHY_TTL_EN(0);
dev_err(&pdev->dev, "ioremap mipi-lvds ctl reg failed\n");
return PTR_ERR(lvds->ctrl_reg);
}
-
+ if (lvds->data->soc_type == LVDS_SOC_RK3368) {
+ lvds->grf_lvds_base =
+ syscon_regmap_lookup_by_phandle(np, "rockchip,grf");
+ if (IS_ERR(lvds->grf_lvds_base)) {
+ dev_err(&pdev->dev, "can't find rockchip,grf property\n");
+ return PTR_ERR(lvds->grf_lvds_base);
+ }
+ }
ret = rk31xx_lvds_clk_init(lvds);
if(ret < 0)
goto err_clk_init;
#define _RK31XX_LVDS_H_
#include <linux/rk_screen.h>
-
+#include <linux/mfd/syscon.h>
+#include <linux/regmap.h>
#define BITS(x, bit) ((x) << (bit))
#define BITS_MASK(x, mask, bit) BITS((x) & (mask), bit)
#define v_LANE1_EN(x) BITS_MASK(x, 1, 6)
#define v_LANE0_EN(x) BITS_MASK(x, 1, 7)
+#define GRF_SOC_CON7_LVDS 0x041c
enum {
LVDS_SOC_RK312X,
LVDS_SOC_RK3368
struct device *dev;
void __iomem *regbase;
void __iomem *ctrl_reg;
+ struct regmap *grf_lvds_base;
struct clk *pclk; /*phb clk*/
struct clk *ctrl_pclk; /* mipi ctrl pclk*/
struct clk *ctrl_hclk; /* mipi ctrl hclk*/