clk: shmobile: rcar-gen2: Fix qspi divisor
authorLaurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Tue, 7 Jan 2014 16:47:53 +0000 (17:47 +0100)
committerMike Turquette <mturquette@linaro.org>
Wed, 19 Feb 2014 05:41:03 +0000 (21:41 -0800)
The qspi clock divisor is incorrectly set to twice the value it should
have, possibly because it has been computed based on PLL1 as the clock
parent instead of PLL1 / 2 (the datasheets specifies the qspi nominal
frequencies, not the divisor values). Fix it.

Reported-by: Geert Uytterhoeven <geert@linux-m68k.org>
Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Tested-by: Geert Uytterhoeven <geert@linux-m68k.org>
Acked-by: Simon Horman <horms+renesas@verge.net.au>
Signed-off-by: Mike Turquette <mturquette@linaro.org>
drivers/clk/shmobile/clk-rcar-gen2.c

index 8c7bcbd727df3ae6ccdf0b72bdc1ec2f23211fc1..dd272a0d144664aff0012ab109b99f41c1aa2446 100644 (file)
@@ -215,7 +215,7 @@ rcar_gen2_cpg_register_clock(struct device_node *np, struct rcar_gen2_cpg *cpg,
        } else if (!strcmp(name, "qspi")) {
                parent_name = "pll1_div2";
                div = (cpg_mode & (BIT(3) | BIT(2) | BIT(1))) == BIT(2)
-                   ? 16 : 20;
+                   ? 8 : 10;
        } else if (!strcmp(name, "sdh")) {
                parent_name = "pll1_div2";
                table = cpg_sdh_div_table;