mfd: db8500: Update register definition for u8540 clock
authorPhilippe Begnic <philippe.begnic@st.com>
Mon, 27 May 2013 12:41:30 +0000 (14:41 +0200)
committerMike Turquette <mturquette@linaro.org>
Fri, 7 Jun 2013 01:16:41 +0000 (18:16 -0700)
PRCMU and ab8500 registers updated for u8540

Signed-off-by: Philippe Begnic <philippe.begnic@st.com>
Acked-by: Lee Jones <lee.jones@linaro.org>
Signed-off-by: Mike Turquette <mturquette@linaro.org>
include/linux/mfd/abx500/ab8500-sysctrl.h
include/linux/mfd/dbx500-prcmu.h

index 990bc93f46e103f47d42f48108fcf523f19160ff..adba89d9c6601b54eff0d5faffc3e521e71fbb41 100644 (file)
@@ -278,8 +278,8 @@ struct ab8500_sysctrl_platform_data {
 
 #define AB9540_SYSCLK12CONFCTRL_PLL26TO38ENA BIT(0)
 #define AB9540_SYSCLK12CONFCTRL_SYSCLK12USBMUXSEL BIT(1)
-#define AB9540_SYSCLK12CONFCTRL_INT384MHZMUXSEL_MASK 0x0C
-#define AB9540_SYSCLK12CONFCTRL_INT384MHZMUXSEL_SHIFT 2
+#define AB9540_SYSCLK12CONFCTRL_INT384MHZMUXSEL0 BIT(2)
+#define AB9540_SYSCLK12CONFCTRL_INT384MHZMUXSEL1 BIT(3)
 #define AB9540_SYSCLK12CONFCTRL_SYSCLK12BUFMUX BIT(4)
 #define AB9540_SYSCLK12CONFCTRL_SYSCLK12PLLMUX BIT(5)
 #define AB9540_SYSCLK12CONFCTRL_SYSCLK2MUXVALID BIT(6)
index 689e6a0d9c998bfd845e92264fe779fa3b457692..d0ba355cc55f181ebb2f89954c22bddac129930b 100644 (file)
@@ -134,6 +134,10 @@ enum prcmu_clock {
        PRCMU_SIACLK,
        PRCMU_SVACLK,
        PRCMU_ACLK,
+       PRCMU_HVACLK, /* Ux540 only */
+       PRCMU_G1CLK, /* Ux540 only */
+       PRCMU_SDMMCHCLK,
+       PRCMU_CAMCLK,
        PRCMU_NUM_REG_CLOCKS,
        PRCMU_SYSCLK = PRCMU_NUM_REG_CLOCKS,
        PRCMU_CDCLK,
@@ -148,6 +152,13 @@ enum prcmu_clock {
        PRCMU_DSI0ESCCLK,
        PRCMU_DSI1ESCCLK,
        PRCMU_DSI2ESCCLK,
+       /* LCD DSI PLL - Ux540 only */
+       PRCMU_PLLDSI_LCD,
+       PRCMU_DSI0CLK_LCD,
+       PRCMU_DSI1CLK_LCD,
+       PRCMU_DSI0ESCCLK_LCD,
+       PRCMU_DSI1ESCCLK_LCD,
+       PRCMU_DSI2ESCCLK_LCD,
 };
 
 /**