clk: rockchip: rk3366: modify cpuclk_rate_table

add 1296MHz, 1104MHz and 216MHz to the cpuclk_rate_table list

Change-Id: I1ea7ee432b7c69b89cb3c11a74e67d9d6af1a5dd
Signed-off-by: Feng Xiao <xf@rock-chips.com>

diff --git a/drivers/clk/rockchip/clk-rk3366.c b/drivers/clk/rockchip/clk-rk3366.c
index 51ef4ce37b6756db43a415199afed0e41fe762e4..6997403770ac5c8aa69a5a6e0aea19373a4cc762 100644 (file)
--- a/drivers/clk/rockchip/clk-rk3366.c
+++ b/drivers/clk/rockchip/clk-rk3366.c
@@ -190,13 +190,16 @@ static struct rockchip_cpuclk_rate_table rk3366_cpuclk_rates[] __initdata = {
        RK3366_CPUCLK_RATE(1512000000, 1, 5, 5),
        RK3366_CPUCLK_RATE(1488000000, 1, 4, 4),
        RK3366_CPUCLK_RATE(1416000000, 1, 4, 4),
+       RK3366_CPUCLK_RATE(1296000000, 1, 4, 4),
        RK3366_CPUCLK_RATE(1200000000, 1, 3, 3),
+       RK3366_CPUCLK_RATE(1104000000, 1, 3, 3),
        RK3366_CPUCLK_RATE(1008000000, 1, 3, 3),
        RK3366_CPUCLK_RATE( 816000000, 1, 2, 2),
        RK3366_CPUCLK_RATE( 696000000, 1, 2, 2),
        RK3366_CPUCLK_RATE( 600000000, 1, 1, 1),
        RK3366_CPUCLK_RATE( 408000000, 1, 1, 1),
        RK3366_CPUCLK_RATE( 312000000, 1, 1, 1),
+       RK3366_CPUCLK_RATE( 216000000, 1, 1, 1),
 };
 
 static struct rockchip_clk_branch rk3366_i2s_8ch_fracmux __initdata =