RK292X/RK30/RK31:add new process of DDR change frequency

diff --git a/arch/arm/mach-rk2928/board-rk2928-tb.c b/arch/arm/mach-rk2928/board-rk2928-tb.c
index 9c0dcdb20ab54cd7ec5825856d4f38c15c8ca93e..e710a96b1c33016dfc61277c3ede95a134af59a1 100755 (executable)
--- a/arch/arm/mach-rk2928/board-rk2928-tb.c
+++ b/arch/arm/mach-rk2928/board-rk2928-tb.c
@@ -1105,8 +1105,9 @@ static struct cpufreq_frequency_table dvfs_gpu_table[] = {
 };
 
 static struct cpufreq_frequency_table dvfs_ddr_table[] = {
-       {.frequency = 300 * 1000,       .index = 1050 * 1000},
-       {.frequency = 400 * 1000,       .index = 1125 * 1000},
+        {.frequency = 200 * 1000 + DDR_FREQ_SUSPEND,       .index = 1050 * 1000},
+       {.frequency = 300 * 1000 + DDR_FREQ_VIDEO,      .index = 1050 * 1000},
+       {.frequency = 400 * 1000 + DDR_FREQ_NORMAL,     .index = 1125 * 1000},
        {.frequency = CPUFREQ_TABLE_END},
 };
 

diff --git a/arch/arm/mach-rk2928/cpufreq.c b/arch/arm/mach-rk2928/cpufreq.c
index e4850ccd95838f00759ae99a916d4a980bd548bb..b0db6d34fc1bdbc623edc49e02d766abb5c83c73 100755 (executable)
--- a/arch/arm/mach-rk2928/cpufreq.c
+++ b/arch/arm/mach-rk2928/cpufreq.c
@@ -222,14 +222,6 @@ static int rk30_verify_speed(struct cpufreq_policy *policy)
        return cpufreq_frequency_table_verify(policy, freq_table);
 }
 
-static int ddr_scale_rate_for_dvfs(struct clk *clk, unsigned long rate, dvfs_set_rate_callback set_rate)
-{
-       #if defined (CONFIG_DDR_FREQ)
-       ddr_set_rate(rate/(1000*1000));
-       #endif
-       return 0;
-}
-
 static int rk30_cpu_init(struct cpufreq_policy *policy)
 {
        if (policy->cpu == 0) {
@@ -273,10 +265,7 @@ static int rk30_cpu_init(struct cpufreq_policy *policy)
 
                ddr_clk = clk_get(NULL, "ddr");
                if (!IS_ERR(ddr_clk))
-               {
-                       dvfs_clk_register_set_rate_callback(ddr_clk, ddr_scale_rate_for_dvfs);
                        clk_enable_dvfs(ddr_clk);
-               }
 
                aclk_vepu_clk = clk_get(NULL, "aclk_vepu");
                if (!IS_ERR(aclk_vepu_clk))

diff --git a/arch/arm/mach-rk2928/ddr.c b/arch/arm/mach-rk2928/ddr.c
index 036e33c7b6efb0079781f5d9c53fe0dd9eb4b334..99c9c794c34b8698ea7ba001eb77413e3f43107f 100755 (executable)
--- a/arch/arm/mach-rk2928/ddr.c
+++ b/arch/arm/mach-rk2928/ddr.c
@@ -2210,11 +2210,11 @@ int ddr_init(uint32_t dram_speed_bin, uint32_t freq)
     uint32_t cs,die=1;
     uint32_t calStatusLeft, calStatusRight;
 
-    ddr_print("version 1.00 20121009 \n");
+    ddr_print("version 1.00 20130124 \n");
     cs = (1 << (((pGRF_Reg->GRF_OS_REG[1]) >> DDR_RANK_COUNT)&0x1));    //case 0:1rank ; case 1:2rank ;                            
     mem_type = ((pGRF_Reg->GRF_OS_REG[1] >> 13) &0x7);
     ddr_speed_bin = dram_speed_bin;
-    ddr_freq = freq;
+    ddr_freq = 0;
     ddr_sr_idle = 0;
     ddr_dll_status = DDR3_DLL_DISABLE;
 
@@ -2241,9 +2241,14 @@ int ddr_init(uint32_t dram_speed_bin, uint32_t freq)
                                                                     ddr_get_col(), \
                                                                     (ddr_get_cap()>>20));
     ddr_adjust_config(mem_type);
-    value=ddr_change_freq(freq);
+
+    if(freq != 0)
+        value=ddr_change_freq(freq);
+    else
+        value=ddr_change_freq(clk_get_rate(clk_get(NULL, "ddr_pll"))/1000000);
+
     clk_set_rate(clk_get(NULL, "ddr_pll"), 0);
-    ddr_print("init success!!! freq=%dMHz\n", value);
+    ddr_print("init success!!! freq=%dMHz\n", clk_get_rate(clk_get(NULL, "ddr_pll"))/1000000);
 
     calStatusLeft = pPHY_Reg->PHY_REG60;
     calStatusRight = pPHY_Reg->PHY_REG61;

diff --git a/arch/arm/mach-rk30/board-rk30-sdk.c b/arch/arm/mach-rk30/board-rk30-sdk.c
index 3f98b9433832b2bf5e15612c687619c7b1944d24..4e220462ff47f43702b817b30b730024522dfdb7 100755 (executable)
--- a/arch/arm/mach-rk30/board-rk30-sdk.c
+++ b/arch/arm/mach-rk30/board-rk30-sdk.c
@@ -1885,8 +1885,9 @@ static struct cpufreq_frequency_table dvfs_gpu_table[] = {
 };
 
 static struct cpufreq_frequency_table dvfs_ddr_table[] = {
-       {.frequency = 300 * 1000,       .index = 1050 * 1000},
-       {.frequency = 400 * 1000,       .index = 1125 * 1000},
+    {.frequency = 200 * 1000 + DDR_FREQ_SUSPEND, .index = 1050 * 1000},
+       {.frequency = 300 * 1000 + DDR_FREQ_VIDEO, .index = 1050 * 1000},
+       {.frequency = 400 * 1000 + DDR_FREQ_NORMAL, .index = 1125 * 1000},
        {.frequency = CPUFREQ_TABLE_END},
 };
 

diff --git a/arch/arm/mach-rk30/cpufreq.c b/arch/arm/mach-rk30/cpufreq.c
index e421a64a13384bbadb4ce475789f6850dfe5da42..d16f8c901315e372b4bbc49d9f57da152c81cc57 100755 (executable)
--- a/arch/arm/mach-rk30/cpufreq.c
+++ b/arch/arm/mach-rk30/cpufreq.c
@@ -238,15 +238,6 @@ static int rk30_verify_speed(struct cpufreq_policy *policy)
                return -EINVAL;
        return cpufreq_frequency_table_verify(policy, freq_table);
 }
-
-static int ddr_scale_rate_for_dvfs(struct clk *clk, unsigned long rate, dvfs_set_rate_callback set_rate)
-{
-       #if defined (CONFIG_DDR_FREQ)
-       ddr_set_rate(rate/(1000*1000));
-       #endif
-       return 0;
-}
-
 static int rk30_cpu_init(struct cpufreq_policy *policy)
 {
        if (policy->cpu == 0) {
@@ -258,11 +249,7 @@ static int rk30_cpu_init(struct cpufreq_policy *policy)
 
                ddr_clk = clk_get(NULL, "ddr");
                if (!IS_ERR(ddr_clk))
-               {
-                       dvfs_clk_register_set_rate_callback(ddr_clk, ddr_scale_rate_for_dvfs);
                        clk_enable_dvfs(ddr_clk);
-                       //clk_set_rate(ddr_clk,clk_get_rate(ddr_clk)-1);
-               }
                
                cpu_clk = clk_get(NULL, "cpu");
                

diff --git a/arch/arm/mach-rk30/ddr.c b/arch/arm/mach-rk30/ddr.c
index 0b903e79cacb99f8a94912c1175a3db1bf9d8fbb..93d4ac606bb49450e1d0bcd3435e5bc3ca38ee42 100755 (executable)
--- a/arch/arm/mach-rk30/ddr.c
+++ b/arch/arm/mach-rk30/ddr.c
@@ -3414,11 +3414,16 @@ int ddr_init(uint32_t dram_speed_bin, uint32_t freq)
     uint32_t cs,die=1;
     uint32_t gsr,dqstr;
 
-    ddr_print("version 1.00 20130124 \n");
+    ddr_print("version 1.00 20130124-2 \n");
 
     mem_type = pPHY_Reg->DCR.b.DDRMD;
     ddr_speed_bin = dram_speed_bin;
-    ddr_freq = freq;
+
+    if(freq != 0)
+        ddr_freq = freq;
+    else
+        ddr_freq = clk_get_rate(clk_get(NULL, "ddr_pll"))/1000000;
+
     ddr_sr_idle = 0;
     switch(mem_type)
     {
@@ -3463,9 +3468,13 @@ int ddr_init(uint32_t dram_speed_bin, uint32_t freq)
                                                                     (ddr_get_cap()>>20));
     ddr_adjust_config(mem_type);
 
-    value=ddr_change_freq(freq);
+    if(freq != 0)
+        value=ddr_change_freq(freq);
+    else
+        value=ddr_change_freq(clk_get_rate(clk_get(NULL, "ddr_pll"))/1000000);
+
     clk_set_rate(clk_get(NULL, "ddr_pll"), 0);
-    ddr_print("init success!!! freq=%dMHz\n", value);
+    ddr_print("init success!!! freq=%dMHz\n", clk_get_rate(clk_get(NULL, "ddr_pll"))/1000000);
 
     for(value=0;value<4;value++)
     {

diff --git a/arch/arm/plat-rk/Kconfig b/arch/arm/plat-rk/Kconfig
index 33bbb511ffcd9a1ff389fa41ef773fedeab13eb4..8c6ab2d1df3061a8e48dca7428701d6f91394b40 100755 (executable)
--- a/arch/arm/plat-rk/Kconfig
+++ b/arch/arm/plat-rk/Kconfig
@@ -82,13 +82,18 @@ config DDR_TYPE_DDR3_DEFAULT
 
 endchoice
 
+config DDR_INIT_CHANGE_FREQ
+       bool "Enable change DDR frequence when ddr_init"
+       default y
+
 config DDR_SDRAM_FREQ
        int "DDR SDRAM frequence (in MHz)"
+       depends on DDR_INIT_CHANGE_FREQ
        default 400
 
 config DDR_FREQ
        bool "Enable DDR frequency scaling"
-       select RK_SRAM_DMA if ARCH_RK30
+       select RK_SRAM_DMA if ARCH_RK30XX
 
 config DDR_TEST
        bool "DDR Test"

diff --git a/arch/arm/plat-rk/ddr_freq.c b/arch/arm/plat-rk/ddr_freq.c
index 453e1ab87c071a23a1bec0a03e8e1e26ba502304..d8c591dee26c0610fb421b186c4b570eca12821f 100644 (file)
--- a/arch/arm/plat-rk/ddr_freq.c
+++ b/arch/arm/plat-rk/ddr_freq.c
@@ -101,7 +101,6 @@ static noinline void ddrfreq_work(unsigned long sys_status)
                cpu = clk_get(NULL, "cpu");
        if (!gpu)
                gpu = clk_get(NULL, "gpu");
-
        dprintk(DEBUG_VERBOSE, "sys_status %02lx\n", sys_status);
        if (ddr.suspend_rate && (s & (1 << SYS_STATUS_SUSPEND))) {
                ddrfreq_mode(true, &ddr.suspend_rate, "suspend");
@@ -309,6 +308,12 @@ CLK_NOTIFIER(pd_rga, RGA);
 CLK_NOTIFIER(pd_cif0, CIF0);
 CLK_NOTIFIER(pd_cif1, CIF1);
 
+static int ddr_scale_rate_for_dvfs(struct clk *clk, unsigned long rate, dvfs_set_rate_callback set_rate)
+{
+        ddr_set_rate(rate/(1000*1000));
+        return 0;
+}
+
 static int ddrfreq_init(void)
 {
        int i, ret;
@@ -327,6 +332,7 @@ static int ddrfreq_init(void)
                pr_err("failed to get ddr clk, error %d\n", ret);
                return ret;
        }
+    dvfs_clk_register_set_rate_callback(ddr.clk, ddr_scale_rate_for_dvfs);
 
        ddr.normal_rate = clk_get_rate(ddr.clk);
 

diff --git a/arch/arm/plat-rk/include/plat/ddr.h b/arch/arm/plat-rk/include/plat/ddr.h
index 8364ded9577e90a15f9a6a88de98a569fafda2f2..faf0fe758d3fbf7702048bfa986abb89e155dba2 100644 (file)
--- a/arch/arm/plat-rk/include/plat/ddr.h
+++ b/arch/arm/plat-rk/include/plat/ddr.h
@@ -22,7 +22,7 @@
 #ifdef CONFIG_DDR_SDRAM_FREQ
 #define DDR_FREQ          (CONFIG_DDR_SDRAM_FREQ)
 #else
-#define DDR_FREQ 360
+#define DDR_FREQ 0
 #endif
 
 #define DDR3_800D   (0)     // 5-5-5