return 0;
}
-#if 0
+/*#if 0
static int rk32_edp_detect_hpd(struct rk32_edp *edp)
{
int timeout_loop = 0;
return 0;
}
-#endif
+#endif*/
+
static int rk32_edp_read_edid(struct rk32_edp *edp)
{
unsigned char edid[EDID_LENGTH * 2];
*/
/* Read Extension Flag, Number of 128-byte EDID extension blocks */
- retval = rk32_edp_read_byte_from_i2c(edp,
- EDID_ADDR, EDID_EXTENSION_FLAG, &extend_block);
+ retval = rk32_edp_read_byte_from_i2c
+ (edp,
+ EDID_ADDR, EDID_EXTENSION_FLAG, &extend_block);
if (retval < 0) {
dev_err(edp->dev, "EDID extension flag failed!\n");
return -EIO;
dev_dbg(edp->dev, "EDID data includes a single extension!\n");
/* Read EDID data */
- retval = rk32_edp_read_bytes_from_i2c(edp,
+ retval = rk32_edp_read_bytes_from_i2c
+ (edp,
EDID_ADDR, EDID_HEADER,
EDID_LENGTH, &edid[EDID_HEADER]);
if (retval != 0) {
}
/* Read additional EDID data */
- retval = rk32_edp_read_bytes_from_i2c(edp,
+ retval = rk32_edp_read_bytes_from_i2c
+ (edp,
EDID_ADDR, EDID_LENGTH,
EDID_LENGTH, &edid[EDID_LENGTH]);
if (retval != 0) {
return 0;
}
- retval = rk32_edp_read_byte_from_dpcd(edp,
- DPCD_TEST_REQUEST, &test_vector);
+ retval = rk32_edp_read_byte_from_dpcd
+ (edp,
+ DPCD_TEST_REQUEST, &test_vector);
if (retval < 0) {
dev_err(edp->dev, "DPCD EDID Read failed!\n");
return retval;
}
if (test_vector & DPCD_TEST_EDID_READ) {
- retval = rk32_edp_write_byte_to_dpcd(edp,
+ retval = rk32_edp_write_byte_to_dpcd
+ (edp,
DPCD_TEST_EDID_CHECKSUM,
edid[EDID_LENGTH + EDID_CHECKSUM]);
if (retval < 0) {
dev_err(edp->dev, "DPCD EDID Write failed!\n");
return retval;
}
- retval = rk32_edp_write_byte_to_dpcd(edp,
+ retval = rk32_edp_write_byte_to_dpcd
+ (edp,
DPCD_TEST_RESPONSE,
DPCD_TEST_EDID_CHECKSUM_WRITE);
if (retval < 0) {
dev_info(edp->dev, "EDID data does not include any extensions.\n");
/* Read EDID data */
- retval = rk32_edp_read_bytes_from_i2c(edp,
+ retval = rk32_edp_read_bytes_from_i2c
+ (edp,
EDID_ADDR, EDID_HEADER,
EDID_LENGTH, &edid[EDID_HEADER]);
if (retval != 0) {
return 0;
}
- retval = rk32_edp_read_byte_from_dpcd(edp,
- DPCD_TEST_REQUEST, &test_vector);
+ retval = rk32_edp_read_byte_from_dpcd
+ (edp,
+ DPCD_TEST_REQUEST, &test_vector);
if (retval < 0) {
dev_err(edp->dev, "DPCD EDID Read failed!\n");
return retval;
}
if (test_vector & DPCD_TEST_EDID_READ) {
- retval = rk32_edp_write_byte_to_dpcd(edp,
- DPCD_TEST_EDID_CHECKSUM,
- edid[EDID_CHECKSUM]);
+ retval = rk32_edp_write_byte_to_dpcd
+ (edp,
+ DPCD_TEST_EDID_CHECKSUM,
+ edid[EDID_CHECKSUM]);
if (retval < 0) {
dev_err(edp->dev, "DPCD EDID Write failed!\n");
return retval;
}
- retval = rk32_edp_write_byte_to_dpcd(edp,
+ retval = rk32_edp_write_byte_to_dpcd
+ (edp,
DPCD_TEST_RESPONSE,
DPCD_TEST_EDID_CHECKSUM_WRITE);
if (retval < 0) {
dev_err(edp->dev, "EDID Read success!\n");
return 0;
}
-
-#if 0
+#define open_t 0
+#if open_t
static int rk32_edp_handle_edid(struct rk32_edp *edp)
{
u8 buf[12];
static int rk32_edp_enable_rx_to_enhanced_mode(struct rk32_edp *edp,
- bool enable)
+ bool enable)
{
u8 data;
int retval;
- retval = rk32_edp_read_byte_from_dpcd(edp,
- DPCD_LANE_CNT_SET, &data);
+ retval = rk32_edp_read_byte_from_dpcd
+ (edp,
+ DPCD_LANE_CNT_SET, &data);
if (retval < 0)
return retval;
if (enable) {
- retval = rk32_edp_write_byte_to_dpcd(edp,
- DPCD_LANE_CNT_SET,
- DPCD_ENHANCED_FRAME_EN |
- DPCD_LANE_COUNT_SET(data));
+ retval = rk32_edp_write_byte_to_dpcd
+ (edp,
+ DPCD_LANE_CNT_SET,
+ DPCD_ENHANCED_FRAME_EN |
+ DPCD_LANE_COUNT_SET(data));
} else {
/*retval = rk32_edp_write_byte_to_dpcd(edp,
DPCD_ADDR_CONFIGURATION_SET, 0);*/
- retval = rk32_edp_write_byte_to_dpcd(edp,
- DPCD_LANE_CNT_SET,
- DPCD_LANE_COUNT_SET(data));
+ retval = rk32_edp_write_byte_to_dpcd
+ (edp,
+ DPCD_LANE_CNT_SET,
+ DPCD_LANE_COUNT_SET(data));
}
return retval;
u8 data;
int retval;
- retval = rk32_edp_read_byte_from_dpcd(edp,
- DPCD_MAX_LANE_CNT, &data);
+ retval = rk32_edp_read_byte_from_dpcd
+ (edp,
+ DPCD_MAX_LANE_CNT, &data);
if (retval < 0)
return retval;
}
#endif
+
#if defined(SW_LT)
static int rk32_edp_training_pattern_dis(struct rk32_edp *edp)
{
rk32_edp_set_training_pattern(edp, DP_NONE);
retval = rk32_edp_write_byte_to_dpcd(edp,
- DPCD_TRAINING_PATTERN_SET,
- DPCD_TRAINING_PATTERN_DISABLED);
+ DPCD_TRAINING_PATTERN_SET,
+ DPCD_TRAINING_PATTERN_DISABLED);
if (retval < 0)
return retval;
}
static void rk32_edp_set_lane_lane_pre_emphasis(struct rk32_edp *edp,
- int pre_emphasis, int lane)
+ int pre_emphasis, int lane)
{
switch (lane) {
case 0:
/* Set sink to D0 (Sink Not Ready) mode. */
retval = rk32_edp_write_byte_to_dpcd(edp, DPCD_SINK_POWER_STATE,
- DPCD_SET_POWER_STATE_D0);
+ DPCD_SET_POWER_STATE_D0);
if (retval < 0) {
dev_err(edp->dev, "failed to set sink device to D0!\n");
return retval;
buf[0] = edp->link_train.link_rate;
buf[1] = edp->link_train.lane_count;
retval = rk32_edp_write_bytes_to_dpcd(edp, DPCD_LINK_BW_SET,
- 2, buf);
+ 2, buf);
if (retval < 0) {
dev_err(edp->dev, "failed to set bandwidth and lane count!\n");
return retval;
/* Set TX pre-emphasis to level1 */
for (lane = 0; lane < lane_count; lane++)
- rk32_edp_set_lane_lane_pre_emphasis(edp,
- PRE_EMPHASIS_LEVEL_1, lane);
+ rk32_edp_set_lane_lane_pre_emphasis
+ (edp,
+ PRE_EMPHASIS_LEVEL_1, lane);
/* Set training pattern 1 */
rk32_edp_set_training_pattern(edp, TRAINING_PTN1);
/* Set RX training pattern */
retval = rk32_edp_write_byte_to_dpcd(edp,
- DPCD_TRAINING_PATTERN_SET,
- DPCD_SCRAMBLING_DISABLED |
- DPCD_TRAINING_PATTERN_1);
+ DPCD_TRAINING_PATTERN_SET,
+ DPCD_SCRAMBLING_DISABLED |
+ DPCD_TRAINING_PATTERN_1);
if (retval < 0) {
dev_err(edp->dev, "failed to set training pattern 1!\n");
return retval;
buf[lane] = DPCD_PRE_EMPHASIS_PATTERN2_LEVEL0 |
DPCD_VOLTAGE_SWING_PATTERN1_LEVEL0;
retval = rk32_edp_write_bytes_to_dpcd(edp,
- DPCD_TRAINING_LANE0_SET,
- lane_count, buf);
+ DPCD_TRAINING_LANE0_SET,
+ lane_count, buf);
if (retval < 0) {
dev_err(edp->dev, "failed to set training lane!\n");
return retval;
}
static unsigned char rk32_edp_get_adjust_request_voltage(u8 adjust_request[2],
- int lane)
+ int lane)
{
int shift = (lane & 1) * 4;
u8 link_value = adjust_request[lane>>1];
}
static void rk32_edp_set_lane_link_training(struct rk32_edp *edp,
- u8 training_lane_set, int lane)
+ u8 training_lane_set, int lane)
{
switch (lane) {
case 0:
}
static unsigned int rk32_edp_get_lane_link_training(
- struct rk32_edp *edp,
- int lane)
+ struct rk32_edp *edp,
+ int lane)
{
u32 reg;
u8 training_lane;
int retval;
- udelay(100);
+ /*udelay(100);*/
+ usleep_range(99, 100);
lane_count = edp->link_train.lane_count;
retval = rk32_edp_read_bytes_from_dpcd(edp,
- DPCD_LANE0_1_STATUS,
- 2, link_status);
+ DPCD_LANE0_1_STATUS,
+ 2, link_status);
if (retval < 0) {
dev_err(edp->dev, "failed to read lane status!\n");
return retval;
rk32_edp_set_training_pattern(edp, TRAINING_PTN2);
for (lane = 0; lane < lane_count; lane++) {
- retval = rk32_edp_read_bytes_from_dpcd(edp,
- DPCD_ADJUST_REQUEST_LANE0_1,
- 2, adjust_request);
+ retval = rk32_edp_read_bytes_from_dpcd
+ (edp,
+ DPCD_ADJUST_REQUEST_LANE0_1,
+ 2, adjust_request);
if (retval < 0) {
dev_err(edp->dev, "failed to read adjust request!\n");
return retval;
edp->link_train.training_lane[lane] = training_lane;
- rk32_edp_set_lane_link_training(edp,
- edp->link_train.training_lane[lane],
- lane);
+ rk32_edp_set_lane_link_training
+ (edp,
+ edp->link_train.training_lane[lane],
+ lane);
}
retval = rk32_edp_write_byte_to_dpcd(edp,
- DPCD_TRAINING_PATTERN_SET,
- DPCD_SCRAMBLING_DISABLED |
- DPCD_TRAINING_PATTERN_2);
+ DPCD_TRAINING_PATTERN_SET,
+ DPCD_SCRAMBLING_DISABLED |
+ DPCD_TRAINING_PATTERN_2);
if (retval < 0) {
dev_err(edp->dev, "failed to set training pattern 2!\n");
return retval;
}
retval = rk32_edp_write_bytes_to_dpcd(edp,
- DPCD_TRAINING_LANE0_SET,
- lane_count,
+ DPCD_TRAINING_LANE0_SET,
+ lane_count,
edp->link_train.training_lane);
if (retval < 0) {
dev_err(edp->dev, "failed to set training lane!\n");
for (lane = 0; lane < lane_count; lane++) {
training_lane = rk32_edp_get_lane_link_training(
edp, lane);
- retval = rk32_edp_read_bytes_from_dpcd(edp,
- DPCD_ADJUST_REQUEST_LANE0_1,
- 2, adjust_request);
+ retval = rk32_edp_read_bytes_from_dpcd
+ (edp,
+ DPCD_ADJUST_REQUEST_LANE0_1,
+ 2, adjust_request);
if (retval < 0) {
dev_err(edp->dev, "failed to read adjust request!\n");
return retval;
(DPCD_PRE_EMPHASIS_GET(training_lane) ==
pre_emphasis)) {
edp->link_train.cr_loop[lane]++;
- if (edp->link_train.cr_loop[lane] == MAX_CR_LOOP) {
+ if (edp->link_train.cr_loop[lane] ==
+ MAX_CR_LOOP) {
dev_err(edp->dev, "CR Max loop\n");
goto reduce_link_rate;
}
edp->link_train.training_lane[lane] = training_lane;
- rk32_edp_set_lane_link_training(edp,
- edp->link_train.training_lane[lane], lane);
+ rk32_edp_set_lane_link_training
+ (edp,
+ edp->link_train.training_lane[lane], lane);
}
- retval = rk32_edp_write_bytes_to_dpcd(edp,
- DPCD_TRAINING_LANE0_SET,
- lane_count,
- edp->link_train.training_lane);
+ retval = rk32_edp_write_bytes_to_dpcd
+ (edp,
+ DPCD_TRAINING_LANE0_SET,
+ lane_count,
+ edp->link_train.training_lane);
if (retval < 0) {
dev_err(edp->dev, "failed to set training lane!\n");
return retval;
u8 training_lane;
int retval;
- udelay(400);
+ /*udelay(400);*/
+ usleep_range(399, 400);
lane_count = edp->link_train.lane_count;
retval = rk32_edp_read_bytes_from_dpcd(edp,
- DPCD_LANE0_1_STATUS,
- 2, link_status);
+ DPCD_LANE0_1_STATUS,
+ 2, link_status);
if (retval < 0) {
dev_err(edp->dev, "failed to read lane status!\n");
return retval;
link_align[0] = link_status[0];
link_align[1] = link_status[1];
- retval = rk32_edp_read_byte_from_dpcd(edp,
- DPCD_LANE_ALIGN_STATUS_UPDATED,
- &link_align[2]);
+ retval = rk32_edp_read_byte_from_dpcd
+ (edp,
+ DPCD_LANE_ALIGN_STATUS_UPDATED,
+ &link_align[2]);
if (retval < 0) {
dev_err(edp->dev, "failed to read lane aligne status!\n");
return retval;
}
for (lane = 0; lane < lane_count; lane++) {
- retval = rk32_edp_read_bytes_from_dpcd(edp,
- DPCD_ADJUST_REQUEST_LANE0_1,
- 2, adjust_request);
+ retval = rk32_edp_read_bytes_from_dpcd
+ (edp,
+ DPCD_ADJUST_REQUEST_LANE0_1,
+ 2, adjust_request);
if (retval < 0) {
dev_err(edp->dev, "failed to read adjust request!\n");
return retval;
}
for (lane = 0; lane < lane_count; lane++)
- rk32_edp_set_lane_link_training(edp,
- edp->link_train.training_lane[lane],
- lane);
-
- retval = rk32_edp_write_bytes_to_dpcd(edp,
- DPCD_TRAINING_LANE0_SET,
- lane_count,
- edp->link_train.training_lane);
+ rk32_edp_set_lane_link_training
+ (edp,
+ edp->link_train.training_lane[lane],
+ lane);
+
+ retval = rk32_edp_write_bytes_to_dpcd
+ (edp,
+ DPCD_TRAINING_LANE0_SET,
+ lane_count,
+ edp->link_train.training_lane);
if (retval < 0) {
dev_err(edp->dev, "failed to set training lane!\n");
return retval;
}
#endif
static int rk32_edp_get_max_rx_bandwidth(struct rk32_edp *edp,
- u8 *bandwidth)
+ u8 *bandwidth)
{
u8 data;
int retval = 0;
* 0x06 = 1.62 Gbps, 0x0a = 2.7 Gbps
*/
retval = rk32_edp_read_byte_from_dpcd(edp,
- DPCD_MAX_LINK_RATE, &data);
+ DPCD_MAX_LINK_RATE, &data);
if (retval < 0)
*bandwidth = 0;
else
*bandwidth = data;
return retval;
-
}
static int rk32_edp_get_max_rx_lane_count(struct rk32_edp *edp,
- u8 *lane_count)
+ u8 *lane_count)
{
u8 data;
int retval;
* 0x01 = 1 lane, 0x02 = 2 lanes, 0x04 = 4 lanes
*/
retval = rk32_edp_read_byte_from_dpcd(edp,
- DPCD_MAX_LANE_CNT, &data);
+ DPCD_MAX_LANE_CNT, &data);
if (retval < 0)
*lane_count = 0;
else
retval = rk32_edp_get_max_rx_bandwidth(edp,
- &edp->link_train.link_rate);
+ &edp->link_train.link_rate);
retval = rk32_edp_get_max_rx_lane_count(edp,
- &edp->link_train.lane_count);
+ &edp->link_train.lane_count);
dev_info(edp->dev, "max link rate:%d.%dGps max number of lanes:%d\n",
- edp->link_train.link_rate * 27/100,
- edp->link_train.link_rate*27%100,
- edp->link_train.lane_count);
+ edp->link_train.link_rate * 27/100,
+ edp->link_train.link_rate*27%100,
+ edp->link_train.lane_count);
if ((edp->link_train.link_rate != LINK_RATE_1_62GBPS) &&
- (edp->link_train.link_rate != LINK_RATE_2_70GBPS)) {
- dev_warn(edp->dev, "Rx Max Link Rate is abnormal :%x !"
- "use default link rate:%d.%dGps\n",
- edp->link_train.link_rate,
- edp->video_info.link_rate*27/100,
- edp->video_info.link_rate*27%100);
+ (edp->link_train.link_rate != LINK_RATE_2_70GBPS)) {
+ dev_warn
+ (edp->dev,
+ "Rx Mx Link Rate is abnormal:%x!default link rate:%d.%dGps\n",
+ edp->link_train.link_rate,
+ edp->video_info.link_rate*27/100,
+ edp->video_info.link_rate*27%100);
edp->link_train.link_rate = edp->video_info.link_rate;
}
if (edp->link_train.lane_count == 0) {
- dev_err(edp->dev, "Rx Max Lane count is abnormal :%x !"
- "use default lanes:%d\n",
- edp->link_train.lane_count,
- edp->video_info.lane_count);
+ dev_err
+ (edp->dev,
+ "Rx Max Lane count is abnormal :%x !use default lanes:%d\n",
+ edp->link_train.lane_count,
+ edp->video_info.lane_count);
edp->link_train.lane_count = edp->video_info.lane_count;
}
if (val)
dev_err(edp->dev, "hw lt err:%d\n", val);
return val;
-
}
#endif
}
static int rk32_edp_config_video(struct rk32_edp *edp,
- struct video_info *video_info)
+ struct video_info *video_info)
{
int retval = 0;
int timeout_loop = 0;
rk32_edp_config_video_slave_mode(edp, video_info);
rk32_edp_set_video_color_format(edp, video_info->color_depth,
- video_info->color_space,
- video_info->dynamic_range,
- video_info->ycbcr_coeff);
+ video_info->color_space,
+ video_info->dynamic_range,
+ video_info->ycbcr_coeff);
if (rk32_edp_get_pll_lock_status(edp) == DP_PLL_UNLOCKED) {
dev_err(edp->dev, "PLL is not locked yet.\n");
return retval;
}
-#if 0
-static int rk32_edp_enable_scramble(struct rk32_edp *edp, bool enable)
-{
- u8 data;
- int retval;
-
- if (enable) {
- rk32_edp_enable_scrambling(edp);
-
- retval = rk32_edp_read_byte_from_dpcd(edp,
- DPCD_TRAINING_PATTERN_SET,
- &data);
- if (retval < 0)
- return retval;
-
- retval = rk32_edp_write_byte_to_dpcd(edp,
- DPCD_TRAINING_PATTERN_SET,
- (u8)(data & ~DPCD_SCRAMBLING_DISABLED));
- if (retval < 0)
- return retval;
- } else {
- rk32_edp_disable_scrambling(edp);
-
- retval = rk32_edp_read_byte_from_dpcd(edp,
- DPCD_TRAINING_PATTERN_SET,
- &data);
- if (retval < 0)
- return retval;
-
- retval = rk32_edp_write_byte_to_dpcd(edp,
- DPCD_TRAINING_PATTERN_SET,
- (u8)(data | DPCD_SCRAMBLING_DISABLED));
- if (retval < 0)
- return retval;
- }
-
- return 0;
-}
-#endif
-
static irqreturn_t rk32_edp_isr(int irq, void *arg)
{
struct rk32_edp *edp = arg;
.disable = rk32_edp_disable,
};
+/*#if 0
+static int rk32_edp_enable_scramble(struct rk32_edp *edp, bool enable)
+{
+ u8 data;
+ int retval;
+
+ if (enable) {
+ rk32_edp_enable_scrambling(edp);
+
+ retval = rk32_edp_read_byte_from_dpcd
+ (edp,
+ DPCD_TRAINING_PATTERN_SET,
+ &data);
+ if (retval < 0)
+ return retval;
+
+ retval = rk32_edp_write_byte_to_dpcd
+ (edp,
+ DPCD_TRAINING_PATTERN_SET,
+ (u8)(data & ~DPCD_SCRAMBLING_DISABLED));
+ if (retval < 0)
+ return retval;
+ } else {
+ rk32_edp_disable_scrambling(edp);
+
+ retval = rk32_edp_read_byte_from_dpcd
+ (edp,
+ DPCD_TRAINING_PATTERN_SET,
+ &data);
+ if (retval < 0)
+ return retval;
+
+ retval = rk32_edp_write_byte_to_dpcd
+ (edp,
+ DPCD_TRAINING_PATTERN_SET,
+ (u8)(data | DPCD_SCRAMBLING_DISABLED));
+ if (retval < 0)
+ return retval;
+ }
+ return 0;
+}
+#endif*/
#if defined(CONFIG_DEBUG_FS)
static int edp_dpcd_debugfs_show(struct seq_file *s, void *v)
int i = 0;
unsigned char buf[12];
struct rk32_edp *edp = s->private;
+
if (!edp) {
dev_err(edp->dev, "no edp device!\n");
return -ENODEV;
rk32_edp_read_bytes_from_dpcd(edp,
- DPCD_SYMBOL_ERR_CONUT_LANE0, 12, buf);
+ DPCD_SYMBOL_ERR_CONUT_LANE0, 12, buf);
for (i = 0; i < 12; i++)
seq_printf(s, "0x%02x>>0x%02x\n", 0x210 + i, buf[i]);
return 0;
}
-static ssize_t edp_dpcd_write (struct file *file, const char __user *buf, size_t count, loff_t *ppos)
-{
+static ssize_t edp_dpcd_write(struct file *file,
+ const char __user *buf,
+ size_t count,
+ loff_t *ppos)
+{
return count;
}
static int edp_edid_debugfs_show(struct seq_file *s, void *v)
{
struct rk32_edp *edp = s->private;
+
if (!edp) {
dev_err(edp->dev, "no edp device!\n");
return -ENODEV;
return 0;
}
-static ssize_t edp_edid_write (struct file *file, const char __user *buf, size_t count, loff_t *ppos)
-{
- struct rk32_edp *edp = ((struct seq_file *)file->private_data)->private;
+static ssize_t edp_edid_write(struct file *file,
+ const char __user *buf,
+ size_t count,
+ loff_t *ppos)
+{
+ struct rk32_edp *edp =
+ ((struct seq_file *)file->private_data)->private;
+
if (!edp) {
dev_err(edp->dev, "no edp device!\n");
return -ENODEV;
{
int i = 0;
struct rk32_edp *edp = s->private;
+
if (!edp) {
dev_err(edp->dev, "no edp device!\n");
return -ENODEV;
return 0;
}
-static ssize_t edp_reg_write (struct file *file, const char __user *buf, size_t count, loff_t *ppos)
-{
+static ssize_t edp_reg_write(struct file *file,
+ const char __user *buf, size_t count,
+ loff_t *ppos)
+{
return count;
}
.release = single_release, \
}
-EDP_DEBUG_ENTRY(dpcd);
+EDP_DEBUG_ENTRY(dpcd);
EDP_DEBUG_ENTRY(edid);
EDP_DEBUG_ENTRY(reg);
#endif
*/
/*edp 24m need sorft reset*/
edp->rst_24m = devm_reset_control_get(&pdev->dev, "edp_24m");
- if (IS_ERR(edp->rst_24m)) {
+ if (IS_ERR(edp->rst_24m))
dev_err(&pdev->dev, "failed to get reset\n");
- }
/* edp ctrl apb bus need sorft reset */
edp->rst_apb = devm_reset_control_get(&pdev->dev, "edp_apb");
- if (IS_ERR(edp->rst_apb)) {
+ if (IS_ERR(edp->rst_apb))
dev_err(&pdev->dev, "failed to get reset\n");
- }
rk32_edp_clk_enable(edp);
if (!support_uboot_display())
rk32_edp_pre_init(edp);
return edp->irq;
}
ret = devm_request_irq(&pdev->dev, edp->irq, rk32_edp_isr, 0,
- dev_name(&pdev->dev), edp);
+ dev_name(&pdev->dev), edp);
if (ret) {
dev_err(&pdev->dev, "cannot claim IRQ %d\n", edp->irq);
return ret;
dev_err(edp->dev, "failed to create debugfs dir for edp!\n");
} else {
debugfs_create_file("dpcd", S_IRUSR, edp->debugfs_dir,
- edp, &edp_dpcd_debugfs_fops);
+ edp, &edp_dpcd_debugfs_fops);
debugfs_create_file("edid", S_IRUSR, edp->debugfs_dir,
- edp, &edp_edid_debugfs_fops);
+ edp, &edp_edid_debugfs_fops);
debugfs_create_file("reg", S_IRUSR, edp->debugfs_dir,
- edp, &edp_reg_debugfs_fops);
+ edp, &edp_reg_debugfs_fops);
}
#endif
static void rk32_edp_shutdown(struct platform_device *pdev)
{
-
}
#if defined(CONFIG_OF)
static void __exit rk32_edp_module_exit(void)
{
-
}
fs_initcall(rk32_edp_module_init);
#define TOTAL_LINE_CFG_H 0x4c
#define ATV_LINE_CFG_L 0x50
#define ATV_LINE_CFG_H 0x54
-#define VF_PORCH_REG 0x58
-#define VSYNC_CFG_REG 0x5c
-#define VB_PORCH_REG 0x60
-#define TOTAL_PIXELL_REG 0x64
-#define TOTAL_PIXELH_REG 0x68
-#define ATV_PIXELL_REG 0x6c
-#define ATV_PIXELH_REG 0x70
-#define HF_PORCHL_REG 0x74
-#define HF_PORCHH_REG 0x78
-#define HSYNC_CFGL_REG 0x7c
-#define HSYNC_CFGH_REG 0x80
-#define HB_PORCHL_REG 0x84
-#define HB_PORCHH_REG 0x88
+#define VF_PORCH_REG 0x58
+#define VSYNC_CFG_REG 0x5c
+#define VB_PORCH_REG 0x60
+#define TOTAL_PIXELL_REG 0x64
+#define TOTAL_PIXELH_REG 0x68
+#define ATV_PIXELL_REG 0x6c
+#define ATV_PIXELH_REG 0x70
+#define HF_PORCHL_REG 0x74
+#define HF_PORCHH_REG 0x78
+#define HSYNC_CFGL_REG 0x7c
+#define HSYNC_CFGH_REG 0x80
+#define HB_PORCHL_REG 0x84
+#define HB_PORCHH_REG 0x88
#define SSC_REG 0x104
#define GRF_EDP_SECURE_EN (1 << 3)
#define EDP_SEL_VOP_LIT (1 << 5)
+/* PSR */
+/*
+#define PANEL_SELF_REFRESH_CAPABILITY_SUPPORTED_AND_VERSION 0x70
+#define PANEL_SELF_REFRESH_CAPABILITIES 0x71
+#define PSR_SUPPORT 0x1
+#define PSR_ENABLE 0x170
+#define SUorPSR_EVENT_STATUS_INDICATOR 0x2007
+#define SINK_DEVICE_PANEL_SELF_REFRESH_STATUS 0x2008
+#define LAST_RECEIVED_PSR_SDP 0x200a
+#define Definition_within_LinkorSink_Device_Power_Control_Field 0x600
+
+#define HB0 0x02F8
+#define HB1 0x02FC
+#define HB2 0x0300
+#define HB3 0x0304
+#define PB0 0x0308
+#define PB1 0x030C
+#define PB2 0x0310
+#define PB3 0x0314
+#define DB0 0x0254
+#define DB1 0x0258
+#define DB2 0x025C
+#define DB3 0x0260
+#define DB4 0x0264
+#define DB5 0x0268
+#define DB6 0x026c
+#define DB7 0x0270
+#define DP_PD 0x012C
+#define IF_TYPE 0x0244
+#define VSC_SHADOW_DB1 0x0320
+#define PSR_FRAME_UPDATA_CTRL 0x0318
+#define SPDIF_AUDIO_CTL_0 0x00D8
+*/
+/* PSR END */
+
enum dp_irq_type {
DP_IRQ_TYPE_HP_CABLE_IN,
DP_IRQ_TYPE_HP_CABLE_OUT,
struct rk32_edp {
- struct device *dev;
- void __iomem *regs;
+ struct device *dev;
+ void __iomem *regs;
struct regmap *grf;
- unsigned int irq;
+ unsigned int irq;
struct clk *pd;
- struct clk *clk_edp; /*clk for edp controller*/
- struct clk *clk_24m; /*clk for edp phy*/
+ struct clk *clk_edp; /*clk for edp controller*/
+ struct clk *clk_24m; /*clk for edp phy*/
struct clk *pclk; /*clk for phb bus*/
struct reset_control *rst_24m;
struct reset_control *rst_apb;
struct video_info video_info;
struct rk_screen screen;
struct fb_monspecs specs;
- bool clk_on;
+ bool clk_on;
bool edp_en;
struct dentry *debugfs_dir;
};
unsigned int reg_addr,
unsigned char data);
int rk32_edp_read_byte_from_dpcd(struct rk32_edp *edp,
- unsigned int reg_addr,
- unsigned char *data);
+ unsigned int reg_addr,
+ unsigned char *data);
int rk32_edp_write_bytes_to_dpcd(struct rk32_edp *edp,
- unsigned int reg_addr,
- unsigned int count,
- unsigned char data[]);
+ unsigned int reg_addr,
+ unsigned int count,
+ unsigned char data[]);
int rk32_edp_read_bytes_from_dpcd(struct rk32_edp *edp,
- unsigned int reg_addr,
- unsigned int count,
- unsigned char data[]);
+ unsigned int reg_addr,
+ unsigned int count,
+ unsigned char data[]);
int rk32_edp_select_i2c_device(struct rk32_edp *edp,
- unsigned int device_addr,
- unsigned int reg_addr);
+ unsigned int device_addr,
+ unsigned int reg_addr);
int rk32_edp_read_byte_from_i2c(struct rk32_edp *edp,
unsigned int device_addr,
unsigned int reg_addr,
unsigned int *data);
int rk32_edp_read_bytes_from_i2c(struct rk32_edp *edp,
- unsigned int device_addr,
- unsigned int reg_addr,
- unsigned int count,
- unsigned char edid[]);
+ unsigned int device_addr,
+ unsigned int reg_addr,
+ unsigned int count,
+ unsigned char edid[]);
void rk32_edp_set_link_bandwidth(struct rk32_edp *edp, u32 bwtype);
void rk32_edp_get_link_bandwidth(struct rk32_edp *edp, u32 *bwtype);
void rk32_edp_set_lane_count(struct rk32_edp *edp, u32 count);
void rk32_edp_get_lane_count(struct rk32_edp *edp, u32 *count);
void rk32_edp_enable_enhanced_mode(struct rk32_edp *edp, bool enable);
void rk32_edp_set_training_pattern(struct rk32_edp *edp,
- enum pattern_set pattern);
+ enum pattern_set pattern);
void rk32_edp_set_lane0_pre_emphasis(struct rk32_edp *edp, u32 level);
void rk32_edp_set_lane1_pre_emphasis(struct rk32_edp *edp, u32 level);
void rk32_edp_set_lane2_pre_emphasis(struct rk32_edp *edp, u32 level);
void rk32_edp_set_lane3_pre_emphasis(struct rk32_edp *edp, u32 level);
void rk32_edp_set_lane0_link_training(struct rk32_edp *edp,
- u32 training_lane);
+ u32 training_lane);
void rk32_edp_set_lane1_link_training(struct rk32_edp *edp,
- u32 training_lane);
+ u32 training_lane);
void rk32_edp_set_lane2_link_training(struct rk32_edp *edp,
- u32 training_lane);
+ u32 training_lane);
void rk32_edp_set_lane3_link_training(struct rk32_edp *edp,
- u32 training_lane);
+ u32 training_lane);
u32 rk32_edp_get_lane0_link_training(struct rk32_edp *edp);
u32 rk32_edp_get_lane1_link_training(struct rk32_edp *edp);
u32 rk32_edp_get_lane2_link_training(struct rk32_edp *edp);
int rk32_edp_init_video(struct rk32_edp *edp);
void rk32_edp_set_video_color_format(struct rk32_edp *edp,
- u32 color_depth,
- u32 color_space,
- u32 dynamic_range,
- u32 coeff);
+ u32 color_depth,
+ u32 color_space,
+ u32 dynamic_range,
+ u32 coeff);
int rk32_edp_is_slave_video_stream_clock_on(struct rk32_edp *edp);
void rk32_edp_set_video_cr_mn(struct rk32_edp *edp,
- enum clock_recovery_m_value_type type,
- u32 m_value,
- u32 n_value);
+ enum clock_recovery_m_value_type type,
+ u32 m_value,
+ u32 n_value);
void rk32_edp_set_video_timing_mode(struct rk32_edp *edp, u32 type);
void rk32_edp_enable_video_master(struct rk32_edp *edp, bool enable);
void rk32_edp_start_video(struct rk32_edp *edp);
int rk32_edp_is_video_stream_on(struct rk32_edp *edp);
void rk32_edp_config_video_slave_mode(struct rk32_edp *edp,
- struct video_info *video_info);
+ struct video_info *video_info);
void rk32_edp_enable_scrambling(struct rk32_edp *edp);
void rk32_edp_disable_scrambling(struct rk32_edp *edp);
void rk32_edp_rx_control(struct rk32_edp *edp, bool enable);
int rk32_edp_bist_cfg(struct rk32_edp *edp);
-void rk32_edp_hw_link_training_en(struct rk32_edp * edp);
+void rk32_edp_hw_link_training_en(struct rk32_edp *edp);
int rk32_edp_get_hw_lt_status(struct rk32_edp *edp);
int rk32_edp_wait_hw_lt_done(struct rk32_edp *edp);
enum dp_irq_type rk32_edp_get_irq_type(struct rk32_edp *edp);
void rk32_edp_clear_hotplug_interrupts(struct rk32_edp *edp);
-#endif
+#endif
\ No newline at end of file
projects / firefly-linux-kernel-4.4.55.git / commitdiff