drm/i915: use pipe bpp in DP link bandwidth calculations

The pipe may be driving various bpp values depending on the display
configuration, so take that into account when calculating link bandwidth
requirements.

Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Keith Packard <keithp@keithp.com>

diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index 391b55f1cc7496e2e313d77332fafb35ecd4aa15..26ce8c0af9b8a0bdd0d65e9a5b7745a3b4a8dcd3 100644 (file)
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -682,7 +682,7 @@ intel_dp_set_m_n(struct drm_crtc *crtc, struct drm_display_mode *mode,
        struct drm_encoder *encoder;
        struct drm_i915_private *dev_priv = dev->dev_private;
        struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
-       int lane_count = 4, bpp = 24;
+       int lane_count = 4;
        struct intel_dp_m_n m_n;
        int pipe = intel_crtc->pipe;
 
@@ -701,7 +701,6 @@ intel_dp_set_m_n(struct drm_crtc *crtc, struct drm_display_mode *mode,
                        break;
                } else if (is_edp(intel_dp)) {
                        lane_count = dev_priv->edp.lanes;
-                       bpp = dev_priv->edp.bpp;
                        break;
                }
        }
@@ -711,7 +710,7 @@ intel_dp_set_m_n(struct drm_crtc *crtc, struct drm_display_mode *mode,
         * the number of bytes_per_pixel post-LUT, which we always
         * set up for 8-bits of R/G/B, or 3 bytes total.
         */
-       intel_dp_compute_m_n(bpp, lane_count,
+       intel_dp_compute_m_n(intel_crtc->bpp, lane_count,
                             mode->clock, adjusted_mode->clock, &m_n);
 
        if (HAS_PCH_SPLIT(dev)) {