imx-drm: match ipu_di_signal_cfg's clk_pol with its description.
authorDenis Carikli <denis@eukrea.com>
Mon, 7 Apr 2014 12:44:43 +0000 (14:44 +0200)
committerRussell King <rmk+kernel@arm.linux.org.uk>
Sat, 26 Apr 2014 10:23:55 +0000 (11:23 +0100)
According to the datasheet, setting the di0_polarity_disp_clk
field in the GENERAL di register sets the output clock polarity
to active high.

Signed-off-by: Denis Carikli <denis@eukrea.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
drivers/staging/imx-drm/ipu-v3/ipu-di.c
drivers/staging/imx-drm/ipuv3-crtc.c

index 82a9ebad697c76b13181d809fa5c53c6d5200f62..849b3e120ef0898e9117d89782db295126cd37cd 100644 (file)
@@ -595,7 +595,7 @@ int ipu_di_init_sync_panel(struct ipu_di *di, struct ipu_di_signal_cfg *sig)
                }
        }
 
-       if (!sig->clk_pol)
+       if (sig->clk_pol)
                di_gen |= DI_GEN_POLARITY_DISP_CLK;
 
        ipu_di_write(di, di_gen, DI_GENERAL);
index c48f640db0061efe76d74c8df09be47cd5fe440a..f2c9cd04004313a64723fd1f0e8b92c099def7a9 100644 (file)
@@ -158,7 +158,7 @@ static int ipu_crtc_mode_set(struct drm_crtc *crtc,
                sig_cfg.Vsync_pol = 1;
 
        sig_cfg.enable_pol = 1;
-       sig_cfg.clk_pol = 1;
+       sig_cfg.clk_pol = 0;
        sig_cfg.width = mode->hdisplay;
        sig_cfg.height = mode->vdisplay;
        sig_cfg.pixel_fmt = out_pixel_fmt;