Expand ret into "CopyToReg;BRIND"

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28559 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/lib/Target/ARM/ARMISelDAGToDAG.cpp b/lib/Target/ARM/ARMISelDAGToDAG.cpp
index 8312d14dca7fc55e10b9afda5a52082a0cb22294..90ffab0158e232dc15b5db12a80c5d8b4ffbeecb 100644 (file)
--- a/lib/Target/ARM/ARMISelDAGToDAG.cpp
+++ b/lib/Target/ARM/ARMISelDAGToDAG.cpp
@@ -28,13 +28,6 @@
 #include <set>
 using namespace llvm;
 
-namespace ARMISD {
-  enum {
-    FIRST_NUMBER = ISD::BUILTIN_OP_END+ARM::INSTRUCTION_LIST_END,
-    RET_FLAG
-  };
-}
-
 namespace {
   class ARMTargetLowering : public TargetLowering {
   public:
@@ -63,11 +56,12 @@ static SDOperand LowerRET(SDOperand Op, SelectionDAG &DAG) {
   case 1:
     return SDOperand(); // ret void is legal
   case 3:
-    Copy = DAG.getCopyToReg(Op.getOperand(0), ARM::R0, Op.getOperand(2), SDOperand());
+    Copy = DAG.getCopyToReg(Op.getOperand(0), ARM::R0, Op.getOperand(1), SDOperand());
     break;
   }
+  SDOperand LR = DAG.getRegister(ARM::R14, MVT::i32);
 
-  return DAG.getNode(ARMISD::RET_FLAG, MVT::Other, Copy, Copy.getValue(1));
+  return DAG.getNode(ISD::BRIND, MVT::Other, Copy, LR);
 }
 
 static SDOperand LowerFORMAL_ARGUMENTS(SDOperand Op, SelectionDAG &DAG) {

diff --git a/lib/Target/ARM/ARMInstrInfo.td b/lib/Target/ARM/ARMInstrInfo.td
index 4ccfa33faf213395da7c8cb6d99d2942602c6b21..c508754f19486737db4aecd66d80b9402db0cfad 100644 (file)
--- a/lib/Target/ARM/ARMInstrInfo.td
+++ b/lib/Target/ARM/ARMInstrInfo.td
@@ -30,10 +30,6 @@ def SDT_ARMCallSeq : SDTypeProfile<0, 1, [ SDTCisVT<0, i32> ]>;
 def callseq_start  : SDNode<"ISD::CALLSEQ_START", SDT_ARMCallSeq, [SDNPHasChain]>;
 def callseq_end    : SDNode<"ISD::CALLSEQ_END",   SDT_ARMCallSeq, [SDNPHasChain]>;
 
-def SDT_ARMRetFlag : SDTypeProfile<0, 0, []>;
-def retflag        : SDNode<"ARMISD::RET_FLAG", SDT_ARMRetFlag,
-                           [SDNPHasChain, SDNPOptInFlag]>;
-
 def ADJCALLSTACKUP : InstARM<(ops i32imm:$amt),
                             "!ADJCALLSTACKUP $amt",
                             [(callseq_end imm:$amt)]>;
@@ -42,11 +38,7 @@ def ADJCALLSTACKDOWN : InstARM<(ops i32imm:$amt),
                                "!ADJCALLSTACKDOWN $amt",
                                [(callseq_start imm:$amt)]>;
 
-//bx supports other registers as operands. So this looks like a
-//hack. Maybe a ret should be expanded to a "branch lr" and bx
-//declared as a regular instruction
-
-def BX: InstARM<(ops), "bx lr", [(retflag)]>;
+def bxr: InstARM<(ops IntRegs:$dst), "bx $dst", [(brind IntRegs:$dst)]>;
 
 def ldr   : InstARM<(ops IntRegs:$dst, IntRegs:$addr),
                      "ldr $dst, [$addr]",