rk610 : lvds bias power ctl

diff --git a/drivers/video/display/lcd/rk610_lcd.c b/drivers/video/display/lcd/rk610_lcd.c
index 4a400b46aa14a54787c1020e3b3c02161bfe9abe..2b4e3b74217b3f56235c78f400099d9b9e135f27 100644 (file)
--- a/drivers/video/display/lcd/rk610_lcd.c
+++ b/drivers/video/display/lcd/rk610_lcd.c
@@ -55,7 +55,7 @@ static int rk610_output_config(struct i2c_client *client,struct rk29fb_screen *s
      if(SCREEN_LVDS == screen->type){\r
         c = LVDS_OUT_CLK_PIN(0) |LVDS_OUT_CLK_PWR_PIN(1) |LVDS_PLL_PWR_PIN(0) \\r
             |LVDS_LANE_IN_FORMAT(DATA_D0_MSB) |LVDS_INPUT_SOURCE(FROM_LCD0_OR_SCL) \\r
-            |LVDS_OUTPUT_FORMAT(screen->hw_format) ; \r
+            |LVDS_OUTPUT_FORMAT(screen->hw_format) | LVDS_BIASE_PWR(1); \r
            rk610_scaler_write_p0_reg(client, LVDS_CON0, &c);\r
         c = LVDS_OUT_ENABLE(0x0) |LVDS_TX_PWR_ENABLE(0x0); \r
            rk610_scaler_write_p0_reg(client, LVDS_CON1, &c);\r

diff --git a/drivers/video/display/lcd/rk610_lcd.h b/drivers/video/display/lcd/rk610_lcd.h
index 06880b3455b377f9f192df3ed1fd1b11914de4f0..3307702b936695669625c09b361e8dd269435d2c 100644 (file)
--- a/drivers/video/display/lcd/rk610_lcd.h
+++ b/drivers/video/display/lcd/rk610_lcd.h
@@ -4,7 +4,42 @@
 #define ENABLE      1\r
 #define DISABLE     0\r
 /*      LVDS config         */\r
-/* LVDS ÍⲿÁ¬Ïß½Ó·¨  */\r
+/*                  LVDS ÍⲿÁ¬Ïß½Ó·¨                       */\r
+/*          LVDS_8BIT_1    LVDS_8BIT_2     LVDS_8BIT_3     LVDS_6BIT\r
+----------------------------------------------------------------------\r
+    TX0     R0              R2              R2              R0\r
+    TX1     R1              R3              R3              R1\r
+    TX2     R2              R4              R4              R2\r
+Y   TX3     R3              R5              R5              R3\r
+0   TX4     R4              R6              R6              R4\r
+    TX6     R5              R7              R7              R5\r
+    TX7     G0              G2              G2              G0\r
+----------------------------------------------------------------------\r
+    TX8     G1              G3              G3              G1\r
+    TX9     G2              G4              G4              G2\r
+Y   TX12    G3              G5              G5              G3\r
+1   TX13    G4              G6              G6              G4\r
+    TX14    G5              G7              G7              G5\r
+    TX15    B0              B2              B2              B0\r
+    TX18    B1              B3              B3              B1\r
+----------------------------------------------------------------------\r
+    TX19    B2              B4              B4              B2\r
+    TX20    B3              B5              B5              B3\r
+    TX21    B4              B6              B6              B4\r
+Y   TX22    B5              B7              B7              B5\r
+2   TX24    HSYNC           HSYNC           HSYNC           HSYNC\r
+    TX25    VSYNC           VSYNC           VSYNC           VSYNC\r
+    TX26    ENABLE          ENABLE          ENABLE          ENABLE\r
+----------------------------------------------------------------------    \r
+    TX27    R6              R0              GND             GND\r
+    TX5     R7              R1              GND             GND\r
+    TX10    G6              G0              GND             GND\r
+Y   TX11    G7              G1              GND             GND\r
+3   TX16    B6              B0              GND             GND\r
+    TX17    B7              B1              GND             GND\r
+    TX23    RSVD            RSVD            RSVD            RSVD\r
+----------------------------------------------------------------------        \r
+*/\r
 #define LVDS_8BIT_1     0x00\r
 #define LVDS_8BIT_2     0x01\r
 #define LVDS_8BIT_3     0x10\r
@@ -44,6 +79,7 @@
 #define LVDS_OUT_CLK_PIN(x)     (((x)&1)<<7)    //clk enable pin, 0: enable\r
 #define LVDS_OUT_CLK_PWR_PIN(x) (((x)&1)<<6)    //clk pwr enable pin, 1: enable \r
 #define LVDS_PLL_PWR_PIN(x)     (((x)&1)<<5)    //pll pwr enable pin, 0:enable \r
+#define LVDS_BIASE_PWR(x)       (((x)&1)<<4)    //0: power down     1: normal work\r
 #define LVDS_LANE_IN_FORMAT(x)  (((x)&1)<<3)    //0: msb on D0  1:msb on D7\r
 #define LVDS_INPUT_SOURCE(x)    (((x)&1)<<2)    //0: from lcd1  1:from lcd0 or scaler\r
 #define LVDS_OUTPUT_FORMAT(x)   (((x)&3)<<0)    //00:8bit format-1  01:8bit format-2  10:8bit format-3   11:6bit format  \r