AVX2: The BLENDPW instruction selects between vectors of v16i16 using an i8

immediate. We can't use it here because the shuffle code does not check that
the lower part of the word is identical to the upper part.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155440 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/lib/Target/X86/X86ISelLowering.cpp b/lib/Target/X86/X86ISelLowering.cpp
index e16367ab42d06ecfe755296676a01452100090ea..8a11b45f0e7180422ca5e650df9966a65899b407 100644 (file)
--- a/lib/Target/X86/X86ISelLowering.cpp
+++ b/lib/Target/X86/X86ISelLowering.cpp
@@ -5443,12 +5443,6 @@ static SDValue LowerVECTOR_SHUFFLEtoBlend(ShuffleVectorSDNode *SVOp,
     ISDNo = X86ISD::BLENDPD;
     OpTy = MVT::v4f64;
     break;
-  case MVT::v16i16:
-    if (!Subtarget->hasAVX2())
-      return SDValue();
-    ISDNo = X86ISD::BLENDPW;
-    OpTy = MVT::v16i16;
-    break;
   }
   assert(ISDNo && "Invalid Op Number");