WebAssemblyISelDAGToDAG.cpp
WebAssemblyISelLowering.cpp
WebAssemblyInstrInfo.cpp
+ WebAssemblyLowerBrUnless.cpp
WebAssemblyMachineFunctionInfo.cpp
WebAssemblyMCInstLower.cpp
WebAssemblyOptimizeReturned.cpp
FunctionPass *createWebAssemblyRegStackify();
FunctionPass *createWebAssemblyRegColoring();
FunctionPass *createWebAssemblyCFGStackify();
+FunctionPass *createWebAssemblyLowerBrUnless();
FunctionPass *createWebAssemblyRegNumbering();
FunctionPass *createWebAssemblyPeephole();
let Defs = [ARGUMENTS] in {
let isBranch = 1, isTerminator = 1, hasCtrlDep = 1 in {
-def BR_IF : I<(outs), (ins I32:$a, bb_op:$dst),
- [(brcond I32:$a, bb:$dst)],
- "br_if \t$a, $dst">;
+// The condition operand is a boolean value which WebAssembly represents as i32.
+def BR_IF : I<(outs), (ins I32:$cond, bb_op:$dst),
+ [(brcond I32:$cond, bb:$dst)],
+ "br_if \t$cond, $dst">;
+let isCodeGenOnly = 1 in
+def BR_UNLESS : I<(outs), (ins I32:$cond, bb_op:$dst), [],
+ "br_unless\t$cond, $dst">;
let isBarrier = 1 in {
def BR : I<(outs), (ins bb_op:$dst),
[(br bb:$dst)],
} // isBarrier = 1
} // isBranch = 1, isTerminator = 1, hasCtrlDep = 1
+} // Defs = [ARGUMENTS]
+
+def : Pat<(brcond (i32 (setne I32:$cond, 0)), bb:$dst),
+ (BR_IF I32:$cond, bb_op:$dst)>;
+def : Pat<(brcond (i32 (seteq I32:$cond, 0)), bb:$dst),
+ (BR_UNLESS I32:$cond, bb_op:$dst)>;
+
+let Defs = [ARGUMENTS] in {
+
// TODO: SelectionDAG's lowering insists on using a pointer as the index for
// jump tables, so in practice we don't ever use TABLESWITCH_I64 in wasm32 mode
// currently.
case WebAssembly::BR_IF:
if (HaveCond)
return true;
+ Cond.push_back(MachineOperand::CreateImm(true));
+ Cond.push_back(MI.getOperand(0));
+ TBB = MI.getOperand(1).getMBB();
+ HaveCond = true;
+ break;
+ case WebAssembly::BR_UNLESS:
+ if (HaveCond)
+ return true;
+ Cond.push_back(MachineOperand::CreateImm(false));
Cond.push_back(MI.getOperand(0));
TBB = MI.getOperand(1).getMBB();
HaveCond = true;
MachineBasicBlock *FBB,
ArrayRef<MachineOperand> Cond,
DebugLoc DL) const {
- assert(Cond.size() <= 1);
-
if (Cond.empty()) {
if (!TBB)
return 0;
return 1;
}
- BuildMI(&MBB, DL, get(WebAssembly::BR_IF)).addOperand(Cond[0]).addMBB(TBB);
+ assert(Cond.size() == 2 && "Expected a flag and a successor block");
+
+ if (Cond[0].getImm()) {
+ BuildMI(&MBB, DL, get(WebAssembly::BR_IF))
+ .addOperand(Cond[1])
+ .addMBB(TBB);
+ } else {
+ BuildMI(&MBB, DL, get(WebAssembly::BR_UNLESS))
+ .addOperand(Cond[1])
+ .addMBB(TBB);
+ }
if (!FBB)
return 1;
bool WebAssemblyInstrInfo::ReverseBranchCondition(
SmallVectorImpl<MachineOperand> &Cond) const {
- assert(Cond.size() == 1);
-
- // TODO: Add branch reversal here... And re-enable MachineBlockPlacementID
- // when we do.
-
- return true;
+ assert(Cond.size() == 2 && "Expected a flag and a successor block");
+ Cond.front() = MachineOperand::CreateImm(!Cond.front().getImm());
+ return false;
}
--- /dev/null
+//===-- WebAssemblyLowerBrUnless.cpp - Lower br_unless --------------------===//
+//
+// The LLVM Compiler Infrastructure
+//
+// This file is distributed under the University of Illinois Open Source
+// License. See LICENSE.TXT for details.
+//
+//===----------------------------------------------------------------------===//
+///
+/// \file
+/// \brief This file lowers br_unless into br_if with an inverted condition.
+///
+/// br_unless is not currently in the spec, but it's very convenient for LLVM
+/// to use. This pass allows LLVM to use it, for now.
+///
+//===----------------------------------------------------------------------===//
+
+#include "WebAssembly.h"
+#include "WebAssemblyMachineFunctionInfo.h"
+#include "WebAssemblySubtarget.h"
+#include "MCTargetDesc/WebAssemblyMCTargetDesc.h"
+#include "llvm/CodeGen/MachineFunctionPass.h"
+#include "llvm/CodeGen/MachineInstrBuilder.h"
+#include "llvm/Support/Debug.h"
+#include "llvm/Support/raw_ostream.h"
+using namespace llvm;
+
+#define DEBUG_TYPE "wasm-lower-br_unless"
+
+namespace {
+class WebAssemblyLowerBrUnless final : public MachineFunctionPass {
+ const char *getPassName() const override {
+ return "WebAssembly Lower br_unless";
+ }
+
+ void getAnalysisUsage(AnalysisUsage &AU) const override {
+ AU.setPreservesCFG();
+ MachineFunctionPass::getAnalysisUsage(AU);
+ }
+
+ bool runOnMachineFunction(MachineFunction &MF) override;
+
+public:
+ static char ID; // Pass identification, replacement for typeid
+ WebAssemblyLowerBrUnless() : MachineFunctionPass(ID) {}
+};
+} // end anonymous namespace
+
+char WebAssemblyLowerBrUnless::ID = 0;
+FunctionPass *llvm::createWebAssemblyLowerBrUnless() {
+ return new WebAssemblyLowerBrUnless();
+}
+
+bool WebAssemblyLowerBrUnless::runOnMachineFunction(MachineFunction &MF) {
+ DEBUG(dbgs() << "********** Lowering br_unless **********\n"
+ "********** Function: "
+ << MF.getName() << '\n');
+
+ auto &MFI = *MF.getInfo<WebAssemblyFunctionInfo>();
+ const auto &TII = *MF.getSubtarget<WebAssemblySubtarget>().getInstrInfo();
+ auto &MRI = MF.getRegInfo();
+
+ for (auto &MBB : MF) {
+ for (auto MII = MBB.begin(); MII != MBB.end(); ) {
+ MachineInstr *MI = &*MII++;
+ if (MI->getOpcode() != WebAssembly::BR_UNLESS)
+ continue;
+
+ unsigned Cond = MI->getOperand(0).getReg();
+ bool Inverted = false;
+
+ // Attempt to invert the condition in place.
+ if (MFI.isVRegStackified(Cond)) {
+ assert(MRI.hasOneDef(Cond));
+ MachineInstr *Def = MRI.getVRegDef(Cond);
+ switch (Def->getOpcode()) {
+ using namespace WebAssembly;
+ case EQ_I32: Def->setDesc(TII.get(NE_I32)); Inverted = true; break;
+ case NE_I32: Def->setDesc(TII.get(EQ_I32)); Inverted = true; break;
+ case GT_S_I32: Def->setDesc(TII.get(LE_S_I32)); Inverted = true; break;
+ case GE_S_I32: Def->setDesc(TII.get(LT_S_I32)); Inverted = true; break;
+ case LT_S_I32: Def->setDesc(TII.get(GE_S_I32)); Inverted = true; break;
+ case LE_S_I32: Def->setDesc(TII.get(GT_S_I32)); Inverted = true; break;
+ case GT_U_I32: Def->setDesc(TII.get(LE_U_I32)); Inverted = true; break;
+ case GE_U_I32: Def->setDesc(TII.get(LT_U_I32)); Inverted = true; break;
+ case LT_U_I32: Def->setDesc(TII.get(GE_U_I32)); Inverted = true; break;
+ case LE_U_I32: Def->setDesc(TII.get(GT_U_I32)); Inverted = true; break;
+ case EQ_I64: Def->setDesc(TII.get(NE_I64)); Inverted = true; break;
+ case NE_I64: Def->setDesc(TII.get(EQ_I64)); Inverted = true; break;
+ case GT_S_I64: Def->setDesc(TII.get(LE_S_I64)); Inverted = true; break;
+ case GE_S_I64: Def->setDesc(TII.get(LT_S_I64)); Inverted = true; break;
+ case LT_S_I64: Def->setDesc(TII.get(GE_S_I64)); Inverted = true; break;
+ case LE_S_I64: Def->setDesc(TII.get(GT_S_I64)); Inverted = true; break;
+ case GT_U_I64: Def->setDesc(TII.get(LE_U_I64)); Inverted = true; break;
+ case GE_U_I64: Def->setDesc(TII.get(LT_U_I64)); Inverted = true; break;
+ case LT_U_I64: Def->setDesc(TII.get(GE_U_I64)); Inverted = true; break;
+ case LE_U_I64: Def->setDesc(TII.get(GT_U_I64)); Inverted = true; break;
+ case EQ_F32: Def->setDesc(TII.get(NE_F32)); Inverted = true; break;
+ case NE_F32: Def->setDesc(TII.get(EQ_F32)); Inverted = true; break;
+ case EQ_F64: Def->setDesc(TII.get(NE_F64)); Inverted = true; break;
+ case NE_F64: Def->setDesc(TII.get(EQ_F64)); Inverted = true; break;
+ default: break;
+ }
+ }
+
+ // If we weren't able to invert the condition in place. Insert an
+ // expression to invert it.
+ if (!Inverted) {
+ unsigned ZeroReg = MRI.createVirtualRegister(&WebAssembly::I32RegClass);
+ MFI.stackifyVReg(ZeroReg);
+ BuildMI(MBB, MI, MI->getDebugLoc(), TII.get(WebAssembly::CONST_I32), ZeroReg)
+ .addImm(0);
+ unsigned Tmp = MRI.createVirtualRegister(&WebAssembly::I32RegClass);
+ MFI.stackifyVReg(Tmp);
+ BuildMI(MBB, MI, MI->getDebugLoc(), TII.get(WebAssembly::EQ_I32), Tmp)
+ .addReg(Cond)
+ .addReg(ZeroReg);
+ Cond = Tmp;
+ Inverted = true;
+ }
+
+ // The br_unless condition has now been inverted. Insert a br_if and
+ // delete the br_unless.
+ assert(Inverted);
+ BuildMI(MBB, MI, MI->getDebugLoc(), TII.get(WebAssembly::BR_IF))
+ .addReg(Cond)
+ .addMBB(MI->getOperand(1).getMBB());
+ MBB.erase(MI);
+ }
+ }
+
+ return true;
+}
// can use $discard instead.
MachineOperand &MO = MI.getOperand(0);
unsigned OldReg = MO.getReg();
- if (OldReg == MI.getOperand(2).getReg()) {
+ if (OldReg == MI.getOperand(3).getReg()) {
unsigned NewReg = MRI.createVirtualRegister(MRI.getRegClass(OldReg));
MO.setReg(NewReg);
MO.setIsDead();
// Fails with: should be run after register allocation.
disablePass(&MachineCopyPropagationID);
- // TODO: Until we get ReverseBranchCondition support, MachineBlockPlacement
- // can create ugly-looking control flow.
- disablePass(&MachineBlockPlacementID);
-
// Run the register coloring pass to reduce the total number of registers.
addPass(createWebAssemblyRegColoring());
}
// Put the CFG in structured form; insert BLOCK and LOOP markers.
addPass(createWebAssemblyCFGStackify());
+ // Lower br_unless into br_if.
+ addPass(createWebAssemblyLowerBrUnless());
+
// Create a mapping from LLVM CodeGen virtual registers to wasm registers.
addPass(createWebAssemblyRegNumbering());
-; RUN: llc < %s -asm-verbose=false | FileCheck %s
+; RUN: llc < %s -asm-verbose=false -disable-block-placement | FileCheck %s
+; RUN: llc < %s -asm-verbose=false | FileCheck -check-prefix=OPT %s
; Test the CFG stackifier pass.
; CHECK-LABEL: test0:
; CHECK: loop
; CHECK: i32.add
+; CHECK-NOT: br
; CHECK: br_if
+; CHECK-NOT: br
; CHECK: call
; CHECK: br BB0_1{{$}}
; CHECK: return{{$}}
+; OPT-LABEL: test0:
+; OPT: loop
+; OPT: i32.add
+; OPT-NOT: br
+; OPT: br_if
+; OPT-NOT: br
+; OPT: call
+; OPT: br BB0_1{{$}}
+; OPT: return{{$}}
define void @test0(i32 %n) {
entry:
br label %header
; CHECK-LABEL: test1:
; CHECK: loop
; CHECK: i32.add
+; CHECK-NOT: br
; CHECK: br_if
+; CHECK-NOT: br
; CHECK: call
; CHECK: br BB1_1{{$}}
; CHECK: return{{$}}
+; OPT-LABEL: test1:
+; OPT: loop
+; OPT: i32.add
+; OPT-NOT: br
+; OPT: br_if
+; OPT-NOT: br
+; OPT: call
+; OPT: br BB1_1{{$}}
+; OPT: return{{$}}
define void @test1(i32 %n) {
entry:
br label %header
; CHECK: block BB2_2{{$}}
; CHECK: br_if {{.*}}, BB2_2{{$}}
; CHECK: BB2_1:
-; CHECK: br_if $pop{{[0-9]+}}, BB2_1{{$}}
+; CHECK: br_if ${{[0-9]+}}, BB2_1{{$}}
; CHECK: BB2_2:
; CHECK: return{{$}}
+; OPT-LABEL: test2:
+; OPT: block BB2_2{{$}}
+; OPT: br_if {{.*}}, BB2_2{{$}}
+; OPT: BB2_1:
+; OPT: br_if ${{[0-9]+}}, BB2_1{{$}}
+; OPT: BB2_2:
+; OPT: return{{$}}
define void @test2(double* nocapture %p, i32 %n) {
entry:
%cmp.4 = icmp sgt i32 %n, 0
; CHECK-LABEL: doublediamond:
; CHECK: block BB3_5{{$}}
; CHECK: block BB3_2{{$}}
-; CHECK: br_if $pop{{[0-9]+}}, BB3_2{{$}}
+; CHECK: br_if $0, BB3_2{{$}}
; CHECK: block BB3_4{{$}}
-; CHECK: br_if $pop{{[0-9]+}}, BB3_4{{$}}
+; CHECK: br_if $1, BB3_4{{$}}
; CHECK: br BB3_5{{$}}
; CHECK: BB3_4:
; CHECK: BB3_5:
; CHECK: return ${{[0-9]+}}{{$}}
+; OPT-LABEL: doublediamond:
+; OPT: block BB3_5{{$}}
+; OPT: block BB3_4{{$}}
+; OPT: br_if {{.*}}, BB3_4{{$}}
+; OPT: block BB3_3{{$}}
+; OPT: br_if {{.*}}, BB3_3{{$}}
+; OPT: br BB3_5{{$}}
+; OPT: BB3_4:
+; OPT: BB3_5:
+; OPT: return ${{[0-9]+}}{{$}}
define i32 @doublediamond(i32 %a, i32 %b, i32* %p) {
entry:
%c = icmp eq i32 %a, 0
; CHECK-LABEL: triangle:
; CHECK: block BB4_2{{$}}
-; CHECK: br_if $pop{{[0-9]+}}, BB4_2{{$}}
+; CHECK: br_if $1, BB4_2{{$}}
; CHECK: BB4_2:
; CHECK: return ${{[0-9]+}}{{$}}
+; OPT-LABEL: triangle:
+; OPT: block BB4_2{{$}}
+; OPT: br_if $1, BB4_2{{$}}
+; OPT: BB4_2:
+; OPT: return ${{[0-9]+}}{{$}}
define i32 @triangle(i32* %p, i32 %a) {
entry:
%c = icmp eq i32 %a, 0
; CHECK-LABEL: diamond:
; CHECK: block BB5_3{{$}}
; CHECK: block BB5_2{{$}}
-; CHECK: br_if $pop{{[0-9]+}}, BB5_2{{$}}
+; CHECK: br_if $1, BB5_2{{$}}
; CHECK: br BB5_3{{$}}
; CHECK: BB5_2:
; CHECK: BB5_3:
; CHECK: return ${{[0-9]+}}{{$}}
+; OPT-LABEL: diamond:
+; OPT: block BB5_3{{$}}
+; OPT: block BB5_2{{$}}
+; OPT: br_if {{.*}}, BB5_2{{$}}
+; OPT: br BB5_3{{$}}
+; OPT: BB5_2:
+; OPT: BB5_3:
+; OPT: return ${{[0-9]+}}{{$}}
define i32 @diamond(i32* %p, i32 %a) {
entry:
%c = icmp eq i32 %a, 0
; CHECK-LABEL: single_block:
; CHECK-NOT: br
; CHECK: return $pop{{[0-9]+}}{{$}}
+; OPT-LABEL: single_block:
+; OPT-NOT: br
+; OPT: return $pop{{[0-9]+}}{{$}}
define i32 @single_block(i32* %p) {
entry:
store volatile i32 0, i32* %p
; CHECK: i32.store $discard=, 0($0), $pop{{[0-9]+}}{{$}}
; CHECK: br BB7_1{{$}}
; CHECK: BB7_2:
+; OPT-LABEL: minimal_loop:
+; OPT-NOT: br
+; OPT: BB7_1:
+; OPT: i32.store $discard=, 0($0), $pop{{[0-9]+}}{{$}}
+; OPT: br BB7_1{{$}}
+; OPT: BB7_2:
define i32 @minimal_loop(i32* %p) {
entry:
store volatile i32 0, i32* %p
; CHECK: br_if $pop{{[0-9]+}}, BB8_1{{$}}
; CHECK: BB8_2:
; CHECK: return ${{[0-9]+}}{{$}}
+; OPT-LABEL: simple_loop:
+; OPT-NOT: br
+; OPT: BB8_1:
+; OPT: loop BB8_2{{$}}
+; OPT: br_if {{.*}}, BB8_1{{$}}
+; OPT: BB8_2:
+; OPT: return ${{[0-9]+}}{{$}}
define i32 @simple_loop(i32* %p, i32 %a) {
entry:
%c = icmp eq i32 %a, 0
; CHECK-LABEL: doubletriangle:
; CHECK: block BB9_4{{$}}
-; CHECK: br_if $pop{{[0-9]+}}, BB9_4{{$}}
+; CHECK: br_if $0, BB9_4{{$}}
; CHECK: block BB9_3{{$}}
-; CHECK: br_if $pop{{[0-9]+}}, BB9_3{{$}}
+; CHECK: br_if $1, BB9_3{{$}}
; CHECK: BB9_3:
; CHECK: BB9_4:
; CHECK: return ${{[0-9]+}}{{$}}
+; OPT-LABEL: doubletriangle:
+; OPT: block BB9_4{{$}}
+; OPT: br_if $0, BB9_4{{$}}
+; OPT: block BB9_3{{$}}
+; OPT: br_if $1, BB9_3{{$}}
+; OPT: BB9_3:
+; OPT: BB9_4:
+; OPT: return ${{[0-9]+}}{{$}}
define i32 @doubletriangle(i32 %a, i32 %b, i32* %p) {
entry:
%c = icmp eq i32 %a, 0
; CHECK-LABEL: ifelse_earlyexits:
; CHECK: block BB10_4{{$}}
; CHECK: block BB10_2{{$}}
-; CHECK: br_if $pop{{[0-9]+}}, BB10_2{{$}}
+; CHECK: br_if $0, BB10_2{{$}}
; CHECK: br BB10_4{{$}}
; CHECK: BB10_2:
-; CHECK: br_if $pop{{[0-9]+}}, BB10_4{{$}}
+; CHECK: br_if $1, BB10_4{{$}}
; CHECK: BB10_4:
; CHECK: return ${{[0-9]+}}{{$}}
+; OPT-LABEL: ifelse_earlyexits:
+; OPT: block BB10_4{{$}}
+; OPT: block BB10_3{{$}}
+; OPT: br_if {{.*}}, BB10_3{{$}}
+; OPT: br_if $1, BB10_4{{$}}
+; OPT: br BB10_4{{$}}
+; OPT: BB10_3:
+; OPT: BB10_4:
+; OPT: return ${{[0-9]+}}{{$}}
define i32 @ifelse_earlyexits(i32 %a, i32 %b, i32* %p) {
entry:
%c = icmp eq i32 %a, 0
; CHECK: loop BB11_7{{$}}
; CHECK: block BB11_6{{$}}
; CHECK: block BB11_3{{$}}
-; CHECK: br_if $pop{{.*}}, BB11_3{{$}}
+; CHECK: br_if $0, BB11_3{{$}}
; CHECK: br BB11_6{{$}}
; CHECK: BB11_3:
; CHECK: block BB11_5{{$}}
-; CHECK: br_if $pop{{.*}}, BB11_5{{$}}
+; CHECK: br_if $1, BB11_5{{$}}
; CHECK: br BB11_6{{$}}
; CHECK: BB11_5:
; CHECK: BB11_6:
; CHECK: br BB11_1{{$}}
; CHECK: BB11_7:
+; OPT-LABEL: doublediamond_in_a_loop:
+; OPT: BB11_1:
+; OPT: loop BB11_7{{$}}
+; OPT: block BB11_6{{$}}
+; OPT: block BB11_5{{$}}
+; OPT: br_if {{.*}}, BB11_5{{$}}
+; OPT: block BB11_4{{$}}
+; OPT: br_if {{.*}}, BB11_4{{$}}
+; OPT: br BB11_6{{$}}
+; OPT: BB11_4:
+; OPT: br BB11_6{{$}}
+; OPT: BB11_5:
+; OPT: BB11_6:
+; OPT: br BB11_1{{$}}
+; OPT: BB11_7:
define i32 @doublediamond_in_a_loop(i32 %a, i32 %b, i32* %p) {
entry:
br label %header
; rearranged to make the stack contiguous.
; CHECK-LABEL: stack_uses:
-; CHECK-NEXT: .param i32{{$}}
+; CHECK-NEXT: .param i32, i32, i32, i32{{$}}
; CHECK-NEXT: .result i32{{$}}
-; CHECK-NEXT: local i32, i32{{$}}
-; CHECK-NEXT: i32.const $1=, 1{{$}}
-; CHECK-NEXT: i32.const $2=, 0{{$}}
-; CHECK-NEXT: i32.and $push0=, $0, $1{{$}}
-; CHECK-NEXT: i32.eq $push1=, $pop0, $2{{$}}
-; CHECK-NEXT: block BB4_2{{$}}
-; CHECK-NEXT: br_if $pop1, BB4_2{{$}}
-; CHECK-NEXT: return $2{{$}}
-; CHECK-NEXT: BB4_2:{{$}}
-; CHECK-NEXT: return $1{{$}}
-define i32 @stack_uses(i32 %x) {
+; CHECK-NEXT: .local i32, i32{{$}}
+; CHECK-NEXT: i32.const $4=, 1{{$}}
+; CHECK-NEXT: i32.const $5=, 2{{$}}
+; CHECK-NEXT: i32.lt_s $push0=, $0, $4{{$}}
+; CHECK-NEXT: i32.lt_s $push1=, $1, $5{{$}}
+; CHECK-NEXT: i32.xor $push4=, $pop0, $pop1{{$}}
+; CHECK-NEXT: i32.lt_s $push2=, $2, $4{{$}}
+; CHECK-NEXT: i32.lt_s $push3=, $3, $5{{$}}
+; CHECK-NEXT: i32.xor $push5=, $pop2, $pop3{{$}}
+; CHECK-NEXT: i32.xor $push6=, $pop4, $pop5{{$}}
+; CHECK-NEXT: i32.ne $push7=, $pop6, $4{{$}}
+; CHECK-NEXT: block BB4_2{{$}}
+; CHECK-NEXT: br_if $pop7, BB4_2{{$}}
+; CHECK-NEXT: i32.const $push8=, 0{{$}}
+; CHECK-NEXT: return $pop8{{$}}
+; CHECK-NEXT: BB4_2:
+; CHECK-NEXT: return $4{{$}}
+define i32 @stack_uses(i32 %x, i32 %y, i32 %z, i32 %w) {
entry:
- %c = trunc i32 %x to i1
- br i1 %c, label %true, label %false
+ %c = icmp sle i32 %x, 0
+ %d = icmp sle i32 %y, 1
+ %e = icmp sle i32 %z, 0
+ %f = icmp sle i32 %w, 1
+ %g = xor i1 %c, %d
+ %h = xor i1 %e, %f
+ %i = xor i1 %g, %h
+ br i1 %i, label %true, label %false
true:
ret i32 0
false:
-; RUN: llc < %s -asm-verbose=false | FileCheck %s
+; RUN: llc < %s -asm-verbose=false -disable-block-placement | FileCheck %s
-; Test switch instructions.
+; Test switch instructions. Block placement is disabled because it reorders
+; the blocks in a way that isn't interesting here.
target datalayout = "e-p:32:32-i64:64-n32:64-S128"
target triple = "wasm32-unknown-unknown"
projects / oota-llvm.git / commitdiff