return;
prm_write_mod_reg(OMAP24XX_VALID_CONFIG, OMAP24XX_GR_MOD,
- OMAP24XX_PRCM_CLKCFG_CTRL_OFFSET);
+ OMAP2_PRCM_CLKCFG_CTRL_OFFSET);
/* OCP barrier */
- prm_read_mod_reg(OMAP24XX_GR_MOD, OMAP24XX_PRCM_CLKCFG_CTRL_OFFSET);
+ prm_read_mod_reg(OMAP24XX_GR_MOD, OMAP2_PRCM_CLKCFG_CTRL_OFFSET);
}
/*
const struct clksel_rate *clkr;
u32 last_div = 0;
- printk(KERN_INFO "clock: clksel_round_rate_div: %s target_rate %ld\n",
- clk->name, target_rate);
+ pr_debug("clock: clksel_round_rate_div: %s target_rate %ld\n",
+ clk->name, target_rate);
*new_div = 1;
/* Sanity check */
if (clkr->div <= last_div)
- printk(KERN_ERR "clock: clksel_rate table not sorted "
+ pr_err("clock: clksel_rate table not sorted "
"for clock %s", clk->name);
last_div = clkr->div;
}
if (!clkr->div) {
- printk(KERN_ERR "clock: Could not find divisor for target "
+ pr_err("clock: Could not find divisor for target "
"rate %ld for clock %s parent %s\n", target_rate,
clk->name, clk->parent->name);
return ~0;
*new_div = clkr->div;
- printk(KERN_INFO "clock: new_div = %d, new_rate = %ld\n", *new_div,
- (clk->parent->rate / clkr->div));
+ pr_debug("clock: new_div = %d, new_rate = %ld\n", *new_div,
+ (clk->parent->rate / clkr->div));
return (clk->parent->rate / clkr->div);
}
if ((regval32 & (1 << clk->enable_bit)) == v)
return;
- printk(KERN_INFO "Disabling unused clock \"%s\"\n", clk->name);
+ printk(KERN_DEBUG "Disabling unused clock \"%s\"\n", clk->name);
if (cpu_is_omap34xx()) {
omap2_clk_enable(clk);
omap2_clk_disable(clk);
CLK(NULL, "mdm_ick", &mdm_ick, CK_243X),
CLK(NULL, "mdm_osc_ck", &mdm_osc_ck, CK_243X),
/* DSS domain clocks */
- CLK(NULL, "dss_ick", &dss_ick, CK_243X | CK_242X),
- CLK(NULL, "dss1_fck", &dss1_fck, CK_243X | CK_242X),
- CLK(NULL, "dss2_fck", &dss2_fck, CK_243X | CK_242X),
- CLK(NULL, "dss_54m_fck", &dss_54m_fck, CK_243X | CK_242X),
+ CLK("omapfb", "ick", &dss_ick, CK_243X | CK_242X),
+ CLK("omapfb", "dss1_fck", &dss1_fck, CK_243X | CK_242X),
+ CLK("omapfb", "dss2_fck", &dss2_fck, CK_243X | CK_242X),
+ CLK("omapfb", "tv_fck", &dss_54m_fck, CK_243X | CK_242X),
/* L3 domain clocks */
CLK(NULL, "core_l3_ck", &core_l3_ck, CK_243X | CK_242X),
CLK(NULL, "ssi_fck", &ssi_ssr_sst_fck, CK_243X | CK_242X),
CLK(NULL, "aes_ick", &aes_ick, CK_243X | CK_242X),
CLK(NULL, "pka_ick", &pka_ick, CK_243X | CK_242X),
CLK(NULL, "usb_fck", &usb_fck, CK_243X | CK_242X),
- CLK(NULL, "usbhs_ick", &usbhs_ick, CK_243X),
+ CLK("musb_hdrc", "ick", &usbhs_ick, CK_243X),
CLK("mmci-omap-hs.0", "ick", &mmchs1_ick, CK_243X),
CLK("mmci-omap-hs.0", "fck", &mmchs1_fck, CK_243X),
CLK("mmci-omap-hs.1", "ick", &mmchs2_ick, CK_243X),
static struct clk *vclk;
static struct clk *sclk;
+static void __iomem *prcm_clksrc_ctrl;
+
/*-------------------------------------------------------------------------
* Omap24xx specific clock functions
*-------------------------------------------------------------------------*/
{
u32 pcc;
- pcc = __raw_readl(OMAP24XX_PRCM_CLKSRC_CTRL);
+ pcc = __raw_readl(prcm_clksrc_ctrl);
- __raw_writel(pcc & ~OMAP_AUTOEXTCLKMODE_MASK,
- OMAP24XX_PRCM_CLKSRC_CTRL);
+ __raw_writel(pcc & ~OMAP_AUTOEXTCLKMODE_MASK, prcm_clksrc_ctrl);
return 0;
}
{
u32 pcc;
- pcc = __raw_readl(OMAP24XX_PRCM_CLKSRC_CTRL);
+ pcc = __raw_readl(prcm_clksrc_ctrl);
- __raw_writel(pcc | OMAP_AUTOEXTCLKMODE_MASK,
- OMAP24XX_PRCM_CLKSRC_CTRL);
+ __raw_writel(pcc | OMAP_AUTOEXTCLKMODE_MASK, prcm_clksrc_ctrl);
}
static const struct clkops clkops_oscck = {
{
u32 div;
- div = __raw_readl(OMAP24XX_PRCM_CLKSRC_CTRL);
+ div = __raw_readl(prcm_clksrc_ctrl);
div &= OMAP_SYSCLKDIV_MASK;
div >>= OMAP_SYSCLKDIV_SHIFT;
struct omap_clk *c;
u32 clkrate;
- if (cpu_is_omap242x())
+ if (cpu_is_omap242x()) {
+ prcm_clksrc_ctrl = OMAP2420_PRCM_CLKSRC_CTRL;
cpu_mask = RATE_IN_242X;
- else if (cpu_is_omap2430())
+ } else if (cpu_is_omap2430()) {
+ prcm_clksrc_ctrl = OMAP2430_PRCM_CLKSRC_CTRL;
cpu_mask = RATE_IN_243X;
+ }
clk_init(&omap2_clk_functions);
for (c = omap24xx_clks; c < omap24xx_clks + ARRAY_SIZE(omap24xx_clks); c++)
- clk_init_one(c->lk.clk);
+ clk_preinit(c->lk.clk);
osc_ck.rate = omap2_osc_clk_recalc(&osc_ck);
propagate_rate(&osc_ck);
CLK(NULL, "ssi_ssr_fck", &ssi_ssr_fck, CK_343X),
CLK(NULL, "ssi_sst_fck", &ssi_sst_fck, CK_343X),
CLK(NULL, "core_l3_ick", &core_l3_ick, CK_343X),
- CLK(NULL, "hsotgusb_ick", &hsotgusb_ick, CK_343X),
+ CLK("musb_hdrc", "ick", &hsotgusb_ick, CK_343X),
CLK(NULL, "sdrc_ick", &sdrc_ick, CK_343X),
CLK(NULL, "gpmc_fck", &gpmc_fck, CK_343X),
CLK(NULL, "security_l3_ick", &security_l3_ick, CK_343X),
CLK("omap_rng", "ick", &rng_ick, CK_343X),
CLK(NULL, "sha11_ick", &sha11_ick, CK_343X),
CLK(NULL, "des1_ick", &des1_ick, CK_343X),
- CLK(NULL, "dss1_alwon_fck", &dss1_alwon_fck, CK_343X),
- CLK(NULL, "dss_tv_fck", &dss_tv_fck, CK_343X),
- CLK(NULL, "dss_96m_fck", &dss_96m_fck, CK_343X),
- CLK(NULL, "dss2_alwon_fck", &dss2_alwon_fck, CK_343X),
- CLK(NULL, "dss_ick", &dss_ick, CK_343X),
+ CLK("omapfb", "dss1_fck", &dss1_alwon_fck, CK_343X),
+ CLK("omapfb", "tv_fck", &dss_tv_fck, CK_343X),
+ CLK("omapfb", "video_fck", &dss_96m_fck, CK_343X),
+ CLK("omapfb", "dss2_fck", &dss2_alwon_fck, CK_343X),
+ CLK("omapfb", "ick", &dss_ick, CK_343X),
CLK(NULL, "cam_mclk", &cam_mclk, CK_343X),
CLK(NULL, "cam_ick", &cam_ick, CK_343X),
CLK(NULL, "csi2_96m_fck", &csi2_96m_fck, CK_343X),
#define MAX_DPLL_WAIT_TRIES 1000000
+ #define MIN_SDRC_DLL_LOCK_FREQ 83000000
+
/**
* omap3_dpll_recalc - recalculate DPLL rate
* @clk: DPLL struct clk
static int omap3_core_dpll_m2_set_rate(struct clk *clk, unsigned long rate)
{
u32 new_div = 0;
+ u32 unlock_dll = 0;
unsigned long validrate, sdrcrate;
struct omap_sdrc_params *sp;
if (!sp)
return -EINVAL;
- pr_info("clock: changing CORE DPLL rate from %lu to %lu\n", clk->rate,
- validrate);
- pr_info("clock: SDRC timing params used: %08x %08x %08x\n",
- sp->rfr_ctrl, sp->actim_ctrla, sp->actim_ctrlb);
+ if (sdrcrate < MIN_SDRC_DLL_LOCK_FREQ) {
+ pr_debug("clock: will unlock SDRC DLL\n");
+ unlock_dll = 1;
+ }
+
+ pr_debug("clock: changing CORE DPLL rate from %lu to %lu\n", clk->rate,
+ validrate);
+ pr_debug("clock: SDRC timing params used: %08x %08x %08x\n",
+ sp->rfr_ctrl, sp->actim_ctrla, sp->actim_ctrlb);
/* REVISIT: SRAM code doesn't support other M2 divisors yet */
WARN_ON(new_div != 1 && new_div != 2);
/* REVISIT: Add SDRC_MR changing to this code also */
omap3_configure_core_dpll(sp->rfr_ctrl, sp->actim_ctrla,
- sp->actim_ctrlb, new_div);
+ sp->actim_ctrlb, new_div, unlock_dll);
return 0;
}
clk_init(&omap2_clk_functions);
for (c = omap34xx_clks; c < omap34xx_clks + ARRAY_SIZE(omap34xx_clks); c++)
- clk_init_one(c->lk.clk);
+ clk_preinit(c->lk.clk);
for (c = omap34xx_clks; c < omap34xx_clks + ARRAY_SIZE(omap34xx_clks); c++)
if (c->cpu & cpu_clkflg) {
base = OMAP3_SRAM_PA;
base = ROUND_DOWN(base, PAGE_SIZE);
omap_sram_io_desc[0].pfn = __phys_to_pfn(base);
+
+ /*
+ * SRAM must be marked as non-cached on OMAP3 since the
+ * CORE DPLL M2 divider change code (in SRAM) runs with the
+ * SDRAM controller disabled, and if it is marked cached,
+ * the ARM may attempt to write cache lines back to SDRAM
+ * which will cause the system to hang.
+ */
+ omap_sram_io_desc[0].type = MT_MEMORY_NONCACHED;
}
omap_sram_io_desc[0].length = 1024 * 1024; /* Use section desc */
return (void *)omap_sram_ceil;
}
-static void omap_sram_error(void)
-{
- panic("Uninitialized SRAM function\n");
-}
-
#ifdef CONFIG_ARCH_OMAP1
static void (*_omap_sram_reprogram_clock)(u32 dpllctl, u32 ckctl);
void omap_sram_reprogram_clock(u32 dpllctl, u32 ckctl)
{
- if (!_omap_sram_reprogram_clock)
- omap_sram_error();
-
+ BUG_ON(!_omap_sram_reprogram_clock);
_omap_sram_reprogram_clock(dpllctl, ckctl);
}
void omap2_sram_ddr_init(u32 *slow_dll_ctrl, u32 fast_dll_ctrl,
u32 base_cs, u32 force_unlock)
{
- if (!_omap2_sram_ddr_init)
- omap_sram_error();
-
+ BUG_ON(!_omap2_sram_ddr_init);
_omap2_sram_ddr_init(slow_dll_ctrl, fast_dll_ctrl,
base_cs, force_unlock);
}
void omap2_sram_reprogram_sdrc(u32 perf_level, u32 dll_val, u32 mem_type)
{
- if (!_omap2_sram_reprogram_sdrc)
- omap_sram_error();
-
+ BUG_ON(!_omap2_sram_reprogram_sdrc);
_omap2_sram_reprogram_sdrc(perf_level, dll_val, mem_type);
}
u32 omap2_set_prcm(u32 dpll_ctrl_val, u32 sdrc_rfr_val, int bypass)
{
- if (!_omap2_set_prcm)
- omap_sram_error();
-
+ BUG_ON(!_omap2_set_prcm);
return _omap2_set_prcm(dpll_ctrl_val, sdrc_rfr_val, bypass);
}
#endif
static u32 (*_omap3_sram_configure_core_dpll)(u32 sdrc_rfr_ctrl,
u32 sdrc_actim_ctrla,
u32 sdrc_actim_ctrlb,
- u32 m2);
+ u32 m2, u32 unlock_dll);
u32 omap3_configure_core_dpll(u32 sdrc_rfr_ctrl, u32 sdrc_actim_ctrla,
- u32 sdrc_actim_ctrlb, u32 m2)
+ u32 sdrc_actim_ctrlb, u32 m2, u32 unlock_dll)
{
- if (!_omap3_sram_configure_core_dpll)
- omap_sram_error();
-
+ BUG_ON(!_omap3_sram_configure_core_dpll);
return _omap3_sram_configure_core_dpll(sdrc_rfr_ctrl,
sdrc_actim_ctrla,
- sdrc_actim_ctrlb, m2);
+ sdrc_actim_ctrlb, m2,
+ unlock_dll);
}
/* REVISIT: Should this be same as omap34xx_sram_init() after off-idle? */
projects / firefly-linux-kernel-4.4.55.git / commitdiff