clk: rockchip: fix up the rockchip_rk3066_pll_clk_set_by_auto func

Change-Id: Id7c561a50a16918c2943f79701ab72c6eaccdc41
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>

diff --git a/drivers/clk/rockchip/clk-pll.c b/drivers/clk/rockchip/clk-pll.c
index 2643341ae869616496ef4a8af5da8139ef711d89..d61d2a170496c69e019c9bb2cfa1f95354764934 100644 (file)
--- a/drivers/clk/rockchip/clk-pll.c
+++ b/drivers/clk/rockchip/clk-pll.c
@@ -243,11 +243,9 @@ rockchip_rk3066_pll_clk_set_by_auto(struct rockchip_clk_pll *pll,
 
        /* output the best PLL setting */
        if ((nr_out <= PLL_NR_MAX) && (no_out > 0)) {
-               if (rate_table->nr && rate_table->nf && rate_table->no) {
-                       rate_table->nr = nr_out;
-                       rate_table->nf = nf_out;
-                       rate_table->no = no_out;
-               }
+               rate_table->nr = nr_out;
+               rate_table->nf = nf_out;
+               rate_table->no = no_out;
        } else {
                return NULL;
        }
@@ -266,7 +264,7 @@ static const struct rockchip_pll_rate_table *rockchip_get_pll_settings(
                        return &rate_table[i];
        }
 
-       if (pll->type == pll_rk3066 || pll->type == pll_rk3328)
+       if (pll->type == pll_rk3066)
                return rockchip_rk3066_pll_clk_set_by_auto(pll, 24 * MHZ, rate);
        else
                return rockchip_pll_clk_set_by_auto(pll, 24 * MHZ, rate);