arm64: dts: rockchip: add isp0 and isp1 config for rk3399

Change-Id: I27d5843f1cf549e145d1950c5c40796c55896bff
Signed-off-by: dalon.zhang <dalon.zhang@rock-chips.com>

diff --git a/arch/arm64/boot/dts/rockchip/rk3399-android.dtsi b/arch/arm64/boot/dts/rockchip/rk3399-android.dtsi
index 80f47a7ccdd031d57ae6b2100af17fd59dfacafb..1a4f919a42126ac7a87c0164f8f7a3cd6e9f492c 100644 (file)
--- a/arch/arm64/boot/dts/rockchip/rk3399-android.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3399-android.dtsi
@@ -304,6 +304,100 @@
                interrupt-names = "vopl_mmu";
        };
 
+       isp0: isp@ff910000 {
+               compatible = "rockchip,rk3399-isp", "rockchip,isp";
+               reg = <0x0 0xff910000 0x0 0x10000>;
+               interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
+               clocks =
+                       <&cru SCLK_CIF_OUT>, <&cru SCLK_CIF_OUT>,
+                       <&cru SCLK_DPHY_TX1RX1_CFG>, <&cru SCLK_MIPIDPHY_REF>,
+                       <&cru ACLK_ISP0_NOC>, <&cru ACLK_ISP0_WRAPPER>,
+                       <&cru HCLK_ISP0_NOC>, <&cru HCLK_ISP0_WRAPPER>,
+                       <&cru SCLK_ISP0>, <&cru SCLK_DPHY_RX0_CFG>;
+               clock-names =
+                       "clk_cif_out", "clk_cif_pll",
+                       "pclk_dphytxrx", "pclk_dphy_ref",
+                       "aclk_isp0_noc", "aclk_isp0_wrapper",
+                       "hclk_isp0_noc", "hclk_isp0_wrapper",
+                       "clk_isp0", "pclk_dphyrx";
+               pinctrl-names =
+                       "cif_clkout","isp_dvp8bit0", "isp_mipi_fl",
+                       "isp_mipi_fl_prefl", "isp_flash_as_gpio",
+                       "isp_flash_as_trigger_out";
+               pinctrl-0 = <&cif_clkout>;
+               pinctrl-1 = <&isp_dvp_d0d7>;
+               pinctrl-2 = <&cif_clkout>;
+               pinctrl-3 = <&cif_clkout &isp_prelight>;
+               pinctrl-4 = <&isp_flash_trigger_as_gpio>;
+               pinctrl-5 = <&isp_flash_trigger>;
+               rockchip,isp,mipiphy = <2>;
+               rockchip,isp,cifphy = <1>;
+               rockchip,isp,dsiphy,reg = <0xff968000 0x8000>;
+               rockchip,grf = <&grf>;
+               rockchip,cru = <&cru>;
+               rockchip,gpios = <&gpio2 12 GPIO_ACTIVE_HIGH>;
+               rockchip,isp,iommu-enable = <1>;
+               power-domains = <&power RK3399_PD_ISP0>;
+               status = "disabled";
+       };
+
+       isp0_mmu {
+               dbgname = "isp0";
+               compatible = "rockchip,isp0_mmu";
+               reg = <0x0 0xff914000 0x0  0x100>,
+                     <0x0 0xff915000 0x0  0x100>;
+               interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
+               interrupt-names = "isp0_mmu";
+       };
+
+       isp1: isp@ff920000 {
+               compatible = "rockchip,rk3399-isp", "rockchip,isp";
+               reg = <0x0 0xff920000 0x0 0x10000>;
+               interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
+               clocks =
+                       <&cru ACLK_ISP1_NOC>, <&cru ACLK_ISP1_WRAPPER>,
+                       <&cru HCLK_ISP1_NOC>, <&cru HCLK_ISP1_WRAPPER>,
+                       <&cru SCLK_ISP1>, <&cru SCLK_CIF_OUT>,
+                       <&cru SCLK_CIF_OUT>, <&cru SCLK_DPHY_TX1RX1_CFG>,
+                       <&cru SCLK_MIPIDPHY_REF>, <&cru PCLK_ISP1_WRAPPER>,
+                       <&cru SCLK_DPHY_RX0_CFG>;
+               clock-names =
+                       "aclk_isp1_noc", "aclk_isp1_wrapper",
+                       "hclk_isp1_noc", "hclk_isp1_wrapper",
+                       "clk_isp1", "clk_cif_out",
+                       "clk_cif_pll", "pclk_dphytxrx",
+                       "pclk_dphy_ref", "pclk_isp1",
+                       "pclk_dphyrx";
+               pinctrl-names =
+                       "cif_clkout","isp_dvp8bit0", "isp_mipi_fl",
+                       "isp_mipi_fl_prefl", "isp_flash_as_gpio",
+                       "isp_flash_as_trigger_out";
+               pinctrl-0 = <&cif_clkout>;
+               pinctrl-1 = <&cif_clkout &isp_dvp_d0d7>;
+               pinctrl-2 = <&cif_clkout>;
+               pinctrl-3 = <&cif_clkout &isp_prelight>;
+               pinctrl-4 = <&isp_flash_trigger_as_gpio>;
+               pinctrl-5 = <&isp_flash_trigger>;
+               rockchip,isp,mipiphy = <2>;
+               rockchip,isp,cifphy = <1>;
+               rockchip,isp,dsiphy,reg = <0xff968000 0x8000>;
+               rockchip,grf = <&grf>;
+               rockchip,cru = <&cru>;
+               rockchip,gpios = <&gpio2 12 GPIO_ACTIVE_HIGH>;
+               rockchip,isp,iommu-enable = <1>;
+               power-domains = <&power RK3399_PD_ISP1>;
+               status = "disabled";
+       };
+
+       isp1_mmu {
+               dbgname = "isp1";
+               compatible = "rockchip,isp1_mmu";
+               reg = <0x0 0xff924000 0x0  0x100>,
+                     <0x0 0xff925000 0x0  0x100>;
+               interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
+               interrupt-names = "isp1_mmu";
+       };
+
        hdmi_rk_fb: hdmi-rk-fb@ff940000 {
                status = "disabled";
                compatible = "rockchip,rk3399-hdmi";
@@ -393,3 +487,64 @@
 &usbdrd_dwc3_0 {
        dr_mode = "peripheral";
 };
+
+&pinctrl {
+       isp {
+               cif_clkout: cif-clkout {
+                       rockchip,pins =
+                       /*cif_clkout*/
+                       <2 11 RK_FUNC_3 &pcfg_pull_none>;
+               };
+
+               isp_dvp_d0d7: isp-dvp-d0d7 {
+                       rockchip,pins =
+                       /*cif_data0*/
+                       <2 0 RK_FUNC_3 &pcfg_pull_none>,
+                       /*cif_data1*/
+                       <2 1 RK_FUNC_3 &pcfg_pull_none>,
+                       /*cif_data2*/
+                       <2 2 RK_FUNC_3 &pcfg_pull_none>,
+                       /*cif_data3*/
+                       <2 3 RK_FUNC_3 &pcfg_pull_none>,
+                       /*cif_data4*/
+                       <2 4 RK_FUNC_3 &pcfg_pull_none>,
+                       /*cif_data5*/
+                       <2 5 RK_FUNC_3 &pcfg_pull_none>,
+                       /*cif_data6*/
+                       <2 6 RK_FUNC_3 &pcfg_pull_none>,
+                       /*cif_data7*/
+                       <2 7 RK_FUNC_3 &pcfg_pull_none>,
+                       /*cif_sync*/
+                       <2 8 RK_FUNC_3 &pcfg_pull_none>,
+                       /*cif_href*/
+                       <2 9 RK_FUNC_3 &pcfg_pull_none>,
+                       /*cif_clkin*/
+                       <2 10 RK_FUNC_3 &pcfg_pull_none>,
+                       /*cif_clkout*/
+                       <2 11 RK_FUNC_3 &pcfg_pull_none>;
+               };
+
+               isp_shutter: isp-shutter {
+                       rockchip,pins =
+                       /*SHUTTEREN*/
+                       <1 1 RK_FUNC_1 &pcfg_pull_none>,
+                       /*SHUTTERTRIG*/
+                       <1 0 RK_FUNC_1 &pcfg_pull_none>;
+               };
+
+               isp_flash_trigger: isp-flash-trigger {
+                       /*ISP_FLASHTRIGOU*/
+                       rockchip,pins = <1 3 RK_FUNC_1 &pcfg_pull_none>;
+               };
+
+               isp_prelight: isp-prelight {
+                       /*ISP_PRELIGHTTRIG*/
+                       rockchip,pins = <1 4 RK_FUNC_1 &pcfg_pull_none>;
+               };
+
+               isp_flash_trigger_as_gpio: isp_flash_trigger_as_gpio {
+                       /*ISP_FLASHTRIGOU*/
+                       rockchip,pins = <0 17 RK_FUNC_GPIO &pcfg_pull_none>;
+               };
+       };
+};