Merge remote-tracking branch 'lsk/v3.10/topic/arm64-crypto' into linux-linaro-lsk

Conflicts:
	arch/arm64/include/asm/arch_timer.h
	arch/arm64/include/asm/hwcap.h
	arch/arm64/include/uapi/asm/hwcap.h
	arch/arm64/kernel/setup.c

diff --cc arch/arm64/include/asm/arch_timer.h
index cb2be3b86c6bd85f2d042341c25e86d1aae2a48d,ec7dd946542d3f8e758a4e0ad9837ce866c36db0..2bff16df74a47a88527c0146becf7799ce664072
--- 1/arch/arm64/include/asm/arch_timer.h
--- 2/arch/arm64/include/asm/arch_timer.h
+++ b/arch/arm64/include/asm/arch_timer.h
@@@ -110,34 -110,44 +110,65 @@@ static inline void arch_timer_set_cntkc
  }
  
  static inline void __cpuinit arch_counter_set_user_access(void)
+ {
+       u32 cntkctl = arch_timer_get_cntkctl();
+ 
+       /* Disable user access to the timers and the physical counter */
+       /* Also disable virtual event stream */
+       cntkctl &= ~(ARCH_TIMER_USR_PT_ACCESS_EN
+                       | ARCH_TIMER_USR_VT_ACCESS_EN
+                       | ARCH_TIMER_VIRT_EVT_EN
+                       | ARCH_TIMER_USR_PCT_ACCESS_EN);
+ 
+       /* Enable user access to the virtual counter */
+       cntkctl |= ARCH_TIMER_USR_VCT_ACCESS_EN;
+ 
+       arch_timer_set_cntkctl(cntkctl);
+ }
+ 
+ static inline void arch_timer_evtstrm_enable(int divider)
+ {
+       u32 cntkctl = arch_timer_get_cntkctl();
+       cntkctl &= ~ARCH_TIMER_EVT_TRIGGER_MASK;
+       /* Set the divider and enable virtual event stream */
+       cntkctl |= (divider << ARCH_TIMER_EVT_TRIGGER_SHIFT)
+                       | ARCH_TIMER_VIRT_EVT_EN;
+       arch_timer_set_cntkctl(cntkctl);
+       elf_hwcap |= HWCAP_EVTSTRM;
+ #ifdef CONFIG_COMPAT
+       compat_elf_hwcap |= COMPAT_HWCAP_EVTSTRM;
+ #endif
+ }
+ 
+ static inline u64 arch_counter_get_cntpct(void)
  {
 -      u64 cval;
 +      u32 cntkctl = arch_timer_get_cntkctl();
  
 -      isb();
 -      asm volatile("mrs %0, cntpct_el0" : "=r" (cval));
 +      /* Disable user access to the timers and the physical counter */
 +      /* Also disable virtual event stream */
 +      cntkctl &= ~(ARCH_TIMER_USR_PT_ACCESS_EN
 +                      | ARCH_TIMER_USR_VT_ACCESS_EN
 +                      | ARCH_TIMER_VIRT_EVT_EN
 +                      | ARCH_TIMER_USR_PCT_ACCESS_EN);
  
 -      return cval;
 +      /* Enable user access to the virtual counter */
 +      cntkctl |= ARCH_TIMER_USR_VCT_ACCESS_EN;
 +
 +      arch_timer_set_cntkctl(cntkctl);
 +}
 +
 +static inline void arch_timer_evtstrm_enable(int divider)
 +{
 +      u32 cntkctl = arch_timer_get_cntkctl();
 +      cntkctl &= ~ARCH_TIMER_EVT_TRIGGER_MASK;
 +      /* Set the divider and enable virtual event stream */
 +      cntkctl |= (divider << ARCH_TIMER_EVT_TRIGGER_SHIFT)
 +                      | ARCH_TIMER_VIRT_EVT_EN;
 +      arch_timer_set_cntkctl(cntkctl);
 +      elf_hwcap |= HWCAP_EVTSTRM;
 +#ifdef CONFIG_COMPAT
 +      compat_elf_hwcap |= COMPAT_HWCAP_EVTSTRM;
 +#endif
  }
  
  static inline u64 arch_counter_get_cntvct(void)

diff --cc arch/arm64/include/asm/cputype.h
index e371936b8ab2ed2a66a73a3f148af16bba50a40b,261db2729217a828fbbd194f7d05c9386347645f..c404fb0df3a673710285603c8ba7571fa42a86f8
--- 1/arch/arm64/include/asm/cputype.h
--- 2/arch/arm64/include/asm/cputype.h
+++ b/arch/arm64/include/asm/cputype.h
@@@ -30,19 -20,9 +20,19 @@@
  
  #define MPIDR_HWID_BITMASK    0xff00ffffff
  
 +#define MPIDR_LEVEL_BITS_SHIFT        3
 +#define MPIDR_LEVEL_BITS      (1 << MPIDR_LEVEL_BITS_SHIFT)
 +#define MPIDR_LEVEL_MASK      ((1 << MPIDR_LEVEL_BITS) - 1)
 +
 +#define MPIDR_LEVEL_SHIFT(level) \
 +      (((1 << level) >> 1) << MPIDR_LEVEL_BITS_SHIFT)
 +
 +#define MPIDR_AFFINITY_LEVEL(mpidr, level) \
 +      ((mpidr >> MPIDR_LEVEL_SHIFT(level)) & MPIDR_LEVEL_MASK)
 +
  #define read_cpuid(reg) ({                                            \
        u64 __val;                                                      \
-       asm("mrs        %0, " reg : "=r" (__val));                      \
+       asm("mrs        %0, " #reg : "=r" (__val));                     \
        __val;                                                          \
  })
  

diff --cc arch/arm64/include/asm/hwcap.h
index 6cddbb0c9f5459cff851101fd3010ad74882a1ef,2d96954a60b7b91de243384c4ffb23e4648887f2..024c46183c3cc4bac07977ffcdade60c2567ea98
--- 1/arch/arm64/include/asm/hwcap.h
--- 2/arch/arm64/include/asm/hwcap.h
+++ b/arch/arm64/include/asm/hwcap.h
@@@ -41,9 -47,10 +47,10 @@@
  
  #ifdef CONFIG_COMPAT
  #define COMPAT_ELF_HWCAP      (compat_elf_hwcap)
- extern unsigned int compat_elf_hwcap;
+ #define COMPAT_ELF_HWCAP2     (compat_elf_hwcap2)
+ extern unsigned int compat_elf_hwcap, compat_elf_hwcap2;
  #endif
  
 -extern unsigned int elf_hwcap;
 +extern unsigned long elf_hwcap;
  #endif
  #endif

diff --cc arch/arm64/kernel/setup.c
index 8c7e81c0143faffe664c94b96c972f944641edd5,570af62efb07807c45e42f3a1f56e32392a63df6..05757983626d3f4aa5e6b45a786ad783a8c1f9da
--- 1/arch/arm64/kernel/setup.c
--- 2/arch/arm64/kernel/setup.c
+++ b/arch/arm64/kernel/setup.c
@@@ -213,8 -130,71 +215,71 @@@ static void __init setup_processor(void
        printk("CPU: %s [%08x] revision %d\n",
               cpu_name, read_cpuid_id(), read_cpuid_id() & 15);
  
 -      sprintf(init_utsname()->machine, "aarch64");
 +      sprintf(init_utsname()->machine, ELF_PLATFORM);
        elf_hwcap = 0;
+ 
+       /*
+        * ID_AA64ISAR0_EL1 contains 4-bit wide signed feature blocks.
+        * The blocks we test below represent incremental functionality
+        * for non-negative values. Negative values are reserved.
+        */
+       features = read_cpuid(ID_AA64ISAR0_EL1);
+       block = (features >> 4) & 0xf;
+       if (!(block & 0x8)) {
+               switch (block) {
+               default:
+               case 2:
+                       elf_hwcap |= HWCAP_PMULL;
+               case 1:
+                       elf_hwcap |= HWCAP_AES;
+               case 0:
+                       break;
+               }
+       }
+ 
+       block = (features >> 8) & 0xf;
+       if (block && !(block & 0x8))
+               elf_hwcap |= HWCAP_SHA1;
+ 
+       block = (features >> 12) & 0xf;
+       if (block && !(block & 0x8))
+               elf_hwcap |= HWCAP_SHA2;
+ 
+       block = (features >> 16) & 0xf;
+       if (block && !(block & 0x8))
+               elf_hwcap |= HWCAP_CRC32;
+ 
+ #ifdef CONFIG_COMPAT
+       /*
+        * ID_ISAR5_EL1 carries similar information as above, but pertaining to
+        * the Aarch32 32-bit execution state.
+        */
+       features = read_cpuid(ID_ISAR5_EL1);
+       block = (features >> 4) & 0xf;
+       if (!(block & 0x8)) {
+               switch (block) {
+               default:
+               case 2:
+                       compat_elf_hwcap2 |= COMPAT_HWCAP2_PMULL;
+               case 1:
+                       compat_elf_hwcap2 |= COMPAT_HWCAP2_AES;
+               case 0:
+                       break;
+               }
+       }
+ 
+       block = (features >> 8) & 0xf;
+       if (block && !(block & 0x8))
+               compat_elf_hwcap2 |= COMPAT_HWCAP2_SHA1;
+ 
+       block = (features >> 12) & 0xf;
+       if (block && !(block & 0x8))
+               compat_elf_hwcap2 |= COMPAT_HWCAP2_SHA2;
+ 
+       block = (features >> 16) & 0xf;
+       if (block && !(block & 0x8))
+               compat_elf_hwcap2 |= COMPAT_HWCAP2_CRC32;
+ #endif
  }
  
  static void __init setup_machine_fdt(phys_addr_t dt_phys)