This avoids unnecessary instructions for CPUs which implement the IFAR
(instruction fault address register).
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
.endm
.macro pabt_helper
- mov r0, r4 @ pass address of aborted instruction.
+ @ PABORT handler takes fault address in r4
#ifdef MULTI_PABORT
ldr ip, .LCprocfns
mov lr, pc
/*
* Function: legacy_pabort
*
- * Params : r0 = address of aborted instruction
+ * Params : r4 = address of aborted instruction
*
* Returns : r0 = address of abort
* : r1 = Simulated IFSR with section translation fault status
.align 5
ENTRY(legacy_pabort)
+ mov r0, r4
mov r1, #5
mov pc, lr
ENDPROC(legacy_pabort)
/*
* Function: v6_pabort
*
- * Params : r0 = address of aborted instruction
+ * Params : r4 = address of aborted instruction
*
* Returns : r0 = address of abort
* : r1 = IFSR
.align 5
ENTRY(v6_pabort)
+ mov r0, r4
mrc p15, 0, r1, c5, c0, 1 @ get IFSR
mov pc, lr
ENDPROC(v6_pabort)
/*
* Function: v6_pabort
*
- * Params : r0 = address of aborted instruction
+ * Params : r4 = address of aborted instruction
*
* Returns : r0 = address of abort
* : r1 = IFSR