Provide consistent subreg idx scheme. This (hopefully) fixes remaining divide problems

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76011 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/lib/Target/SystemZ/SystemZISelDAGToDAG.cpp b/lib/Target/SystemZ/SystemZISelDAGToDAG.cpp
index 8ca936f07dfd8902f51091cb55d28117ea4bf2a1..570d35480226219c663da87dd04e431f9f1fe47a 100644 (file)
--- a/lib/Target/SystemZ/SystemZISelDAGToDAG.cpp
+++ b/lib/Target/SystemZ/SystemZISelDAGToDAG.cpp
@@ -30,9 +30,10 @@
 #include "llvm/Support/Debug.h"
 using namespace llvm;
 
-static const unsigned subreg_32bit = 1;
-static const unsigned subreg_even = 1;
-static const unsigned subreg_odd = 2;
+static const unsigned subreg_even32 = 1;
+static const unsigned subreg_odd32  = 2;
+static const unsigned subreg_even   = 3;
+static const unsigned subreg_odd    = 4;
 
 namespace {
   /// SystemZRRIAddressMode - This corresponds to rriaddr, but uses SDValue's
@@ -686,17 +687,13 @@ SDNode *SystemZDAGToDAGISel::Select(SDValue Op) {
 
     // Copy the division (odd subreg) result, if it is needed.
     if (!Op.getValue(0).use_empty()) {
+      unsigned SubRegIdx = (is32Bit ? subreg_odd32 : subreg_odd);
       SDNode *Div = CurDAG->getTargetNode(TargetInstrInfo::EXTRACT_SUBREG,
-                                          dl, (is32Bit ? MVT::v2i32 : MVT::i64),
+                                          dl, NVT,
                                           SDValue(Result, 0),
-                                          CurDAG->getTargetConstant(subreg_odd,
+                                          CurDAG->getTargetConstant(SubRegIdx,
                                                                     MVT::i32));
-      if (is32Bit)
-        Div = CurDAG->getTargetNode(TargetInstrInfo::EXTRACT_SUBREG,
-                                    dl, NVT,
-                                    SDValue(Div, 0),
-                                    CurDAG->getTargetConstant(subreg_32bit,
-                                                              MVT::i32));
+
       ReplaceUses(Op.getValue(0), SDValue(Div, 0));
       #ifndef NDEBUG
       DOUT << std::string(Indent-2, ' ') << "=> ";
@@ -707,17 +704,12 @@ SDNode *SystemZDAGToDAGISel::Select(SDValue Op) {
 
     // Copy the remainder (even subreg) result, if it is needed.
     if (!Op.getValue(1).use_empty()) {
+      unsigned SubRegIdx = (is32Bit ? subreg_even32 : subreg_even);
       SDNode *Rem = CurDAG->getTargetNode(TargetInstrInfo::EXTRACT_SUBREG,
-                                          dl, (is32Bit ? MVT::v2i32 : MVT::i64),
+                                          dl, NVT,
                                           SDValue(Result, 0),
-                                          CurDAG->getTargetConstant(subreg_even,
+                                          CurDAG->getTargetConstant(SubRegIdx,
                                                                     MVT::i32));
-      if (is32Bit)
-        Rem = CurDAG->getTargetNode(TargetInstrInfo::EXTRACT_SUBREG,
-                                    dl, NVT,
-                                    SDValue(Rem, 0),
-                                    CurDAG->getTargetConstant(subreg_32bit,
-                                                              MVT::i32));
 
       ReplaceUses(Op.getValue(1), SDValue(Rem, 0));
       #ifndef NDEBUG
@@ -739,12 +731,14 @@ SDNode *SystemZDAGToDAGISel::Select(SDValue Op) {
     SDValue N1 = Node->getOperand(1);
     MVT ResVT;
 
+    bool is32Bit = false;
     switch (NVT.getSimpleVT()) {
       default: assert(0 && "Unsupported VT!");
       case MVT::i32:
         Opc = SystemZ::UDIVREM32r; MOpc = SystemZ::UDIVREM32m;
         ClrOpc = SystemZ::MOV64Pr0_even;
         ResVT = MVT::v2i32;
+        is32Bit = true;
         break;
       case MVT::i64:
         Opc = SystemZ::UDIVREM64r; MOpc = SystemZ::UDIVREM64m;
@@ -762,10 +756,13 @@ SDNode *SystemZDAGToDAGISel::Select(SDValue Op) {
     // Insert prepared dividend into suitable 'subreg'
     SDNode *Tmp = CurDAG->getTargetNode(TargetInstrInfo::IMPLICIT_DEF,
                                         dl, ResVT);
-    Dividend =
-      CurDAG->getTargetNode(TargetInstrInfo::INSERT_SUBREG, dl, ResVT,
-                            SDValue(Tmp, 0), SDValue(Dividend, 0),
-                            CurDAG->getTargetConstant(subreg_odd, MVT::i32));
+    {
+      unsigned SubRegIdx = (is32Bit ? subreg_odd32 : subreg_odd);
+      Dividend =
+        CurDAG->getTargetNode(TargetInstrInfo::INSERT_SUBREG, dl, ResVT,
+                              SDValue(Tmp, 0), SDValue(Dividend, 0),
+                              CurDAG->getTargetConstant(SubRegIdx, MVT::i32));
+    }
 
     // Zero out even subreg
     Dividend = CurDAG->getTargetNode(ClrOpc, dl, ResVT, SDValue(Dividend, 0));
@@ -784,10 +781,11 @@ SDNode *SystemZDAGToDAGISel::Select(SDValue Op) {
 
     // Copy the division (odd subreg) result, if it is needed.
     if (!Op.getValue(0).use_empty()) {
+      unsigned SubRegIdx = (is32Bit ? subreg_odd32 : subreg_odd);
       SDNode *Div = CurDAG->getTargetNode(TargetInstrInfo::EXTRACT_SUBREG,
                                           dl, NVT,
                                           SDValue(Result, 0),
-                                          CurDAG->getTargetConstant(subreg_odd,
+                                          CurDAG->getTargetConstant(SubRegIdx,
                                                                     MVT::i32));
       ReplaceUses(Op.getValue(0), SDValue(Div, 0));
       #ifndef NDEBUG
@@ -799,10 +797,11 @@ SDNode *SystemZDAGToDAGISel::Select(SDValue Op) {
 
     // Copy the remainder (even subreg) result, if it is needed.
     if (!Op.getValue(1).use_empty()) {
+      unsigned SubRegIdx = (is32Bit ? subreg_even32 : subreg_even);
       SDNode *Rem = CurDAG->getTargetNode(TargetInstrInfo::EXTRACT_SUBREG,
                                           dl, NVT,
                                           SDValue(Result, 0),
-                                          CurDAG->getTargetConstant(subreg_even,
+                                          CurDAG->getTargetConstant(SubRegIdx,
                                                                     MVT::i32));
       ReplaceUses(Op.getValue(1), SDValue(Rem, 0));
       #ifndef NDEBUG

diff --git a/lib/Target/SystemZ/SystemZRegisterInfo.td b/lib/Target/SystemZ/SystemZRegisterInfo.td
index 6fbb4cdb87a0e8954d5ea8e177c77d3d411761c4..e1d0b4f969d9e051f346d88b67595db74883aa0a 100644 (file)
--- a/lib/Target/SystemZ/SystemZRegisterInfo.td
+++ b/lib/Target/SystemZ/SystemZRegisterInfo.td
@@ -123,18 +123,20 @@ def F15 : FPR<15, "f15">, DwarfRegNum<[31]>;
 def PSW : SystemZReg<"psw">;
 
 def subreg_32bit  : PatLeaf<(i32 1)>;
-def subreg_even   : PatLeaf<(i32 1)>;
-def subreg_odd    : PatLeaf<(i32 2)>;
+def subreg_even32 : PatLeaf<(i32 1)>;
+def subreg_odd32  : PatLeaf<(i32 2)>;
+def subreg_even   : PatLeaf<(i32 3)>;
+def subreg_odd    : PatLeaf<(i32 4)>;
 
 def : SubRegSet<1, [R0D, R1D,  R2D,  R3D,  R4D,  R5D,  R6D,  R7D,
                     R8D, R9D, R10D, R11D, R12D, R13D, R14D, R15D],
                    [R0W, R1W,  R2W,  R3W,  R4W,  R5W,  R6W,  R7W,
                     R8W, R9W, R10W, R11W, R12W, R13W, R14W, R15W]>;
 
-def : SubRegSet<1, [R0Q, R2Q, R4Q, R6Q, R8Q, R10Q, R12Q, R14Q],
+def : SubRegSet<3, [R0Q, R2Q, R4Q, R6Q, R8Q, R10Q, R12Q, R14Q],
                    [R0D, R2D, R4D, R6D, R8D, R10D, R12D, R14D]>;
 
-def : SubRegSet<2, [R0Q, R2Q, R4Q, R6Q, R8Q, R10Q, R12Q, R14Q],
+def : SubRegSet<4, [R0Q, R2Q, R4Q, R6Q, R8Q, R10Q, R12Q, R14Q],
                    [R1D, R3D, R5D, R7D, R9D, R11D, R13D, R15D]>;
 
 def : SubRegSet<1, [R0P, R2P, R4P, R6P, R8P, R10P, R12P, R14P],
@@ -143,6 +145,12 @@ def : SubRegSet<1, [R0P, R2P, R4P, R6P, R8P, R10P, R12P, R14P],
 def : SubRegSet<2, [R0P, R2P, R4P, R6P, R8P, R10P, R12P, R14P],
                    [R1W, R3W, R5W, R7W, R9W, R11W, R13W, R15W]>;
 
+def : SubRegSet<1, [R0Q, R2Q, R4Q, R6Q, R8Q, R10Q, R12Q, R14Q],
+                   [R0W, R2W, R4W, R6W, R8W, R10W, R12W, R14W]>;
+
+def : SubRegSet<2, [R0Q, R2Q, R4Q, R6Q, R8Q, R10Q, R12Q, R14Q],
+                   [R1W, R3W, R5W, R7W, R9W, R11W, R13W, R15W]>;
+
 /// Register classes
 def GR32 : RegisterClass<"SystemZ", [i32], 32,
    // Volatile registers
@@ -371,7 +379,7 @@ def GR64P : RegisterClass<"SystemZ", [v2i32], 64,
 def GR128 : RegisterClass<"SystemZ", [i128, v2i64], 128,
   [R0Q, R2Q, R4Q, R6Q, R8Q, R10Q, R12Q, R14Q]>
 {
-  let SubRegClassList = [GR64, GR64];
+  let SubRegClassList = [GR32, GR32, GR64, GR64];
   let MethodProtos = [{
     iterator allocation_order_begin(const MachineFunction &MF) const;
     iterator allocation_order_end(const MachineFunction &MF) const;

diff --git a/test/CodeGen/SystemZ/08-DivRem.ll b/test/CodeGen/SystemZ/08-DivRem.ll
index 45cbfea0e0cfe8f1b4cc16fe362c4c273aa9c3fa..8237d0a157224c3ce14f64596e591d419e721b86 100644 (file)
--- a/test/CodeGen/SystemZ/08-DivRem.ll
+++ b/test/CodeGen/SystemZ/08-DivRem.ll
@@ -1,5 +1,5 @@
 ; RUN: llvm-as < %s | llc | grep dsgr  | count 2
-; RUN: llvm-as < %s | llc | grep dr    | count 2
+; RUN: llvm-as < %s | llc | grep dsgfr | count 2
 ; RUN: llvm-as < %s | llc | grep dlr   | count 2
 ; RUN: llvm-as < %s | llc | grep dlgr  | count 2
 

diff --git a/test/CodeGen/SystemZ/08-DivRemMemOp.ll b/test/CodeGen/SystemZ/08-DivRemMemOp.ll
index 41eef36b2da7a610c5596ce1b06b60fb124722e2..c2befb2a1159acabde230e27893a14fc6d83fdbd 100644 (file)
--- a/test/CodeGen/SystemZ/08-DivRemMemOp.ll
+++ b/test/CodeGen/SystemZ/08-DivRemMemOp.ll
@@ -1,7 +1,7 @@
-; RUN: llvm-as < %s | llc | grep {d.%}  | count 2
-; RUN: llvm-as < %s | llc | grep dsg    | count 2
-; RUN: llvm-as < %s | llc | grep {dl.%} | count 2
-; RUN: llvm-as < %s | llc | grep dlg    | count 2
+; RUN: llvm-as < %s | llc | grep {dsgf.%} | count 2
+; RUN: llvm-as < %s | llc | grep {dsg.%}  | count 2
+; RUN: llvm-as < %s | llc | grep {dl.%}   | count 2
+; RUN: llvm-as < %s | llc | grep dlg      | count 2
 
 target datalayout = "E-p:64:64:64-i1:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-f128:128:128"
 target triple = "s390x-unknown-linux-gnu"