rk30: system clock switch to 32.768K in suspend

diff --git a/arch/arm/mach-rk30/Kconfig b/arch/arm/mach-rk30/Kconfig
index b6dec3bf1b8d09c2b432c38b5fba1b3bead203c7..a8f0fdd3ec14f1f38cfa4532ddbb20d9016ffa2c 100755 (executable)
--- a/arch/arm/mach-rk30/Kconfig
+++ b/arch/arm/mach-rk30/Kconfig
@@ -15,4 +15,10 @@ config MACH_RK30_PHONE_LOQUAT
        
 endchoice
 
+menu "support for RK power manage "
+
+config CLK_SWITCH_TO_32K
+        bool "Support clock switch to 32.768k"
+endmenu
+
 endif

diff --git a/arch/arm/mach-rk30/board-rk30-sdk-wm8326.c b/arch/arm/mach-rk30/board-rk30-sdk-wm8326.c
index 92e2480af09cc5b73f1882e11f81003fad7ec335..f84d22640f327cb595769757d9573b0950e28798 100755 (executable)
--- a/arch/arm/mach-rk30/board-rk30-sdk-wm8326.c
+++ b/arch/arm/mach-rk30/board-rk30-sdk-wm8326.c
@@ -737,7 +737,11 @@ void __sramfunc board_pmu_resume(void)
        grf_writel(GPIO6_PB1_DIR_OUT, GRF_GPIO6L_DIR_ADDR);
        grf_writel(GPIO6_PB1_DO_LOW, GRF_GPIO6L_DO_ADDR);     //set gpio6_b1 output high
        grf_writel(GPIO6_PB1_EN_MASK, GRF_GPIO6L_EN_ADDR);
+#ifdef CONFIG_CLK_SWITCH_TO_32K
+       sram_32k_udelay(10000);
+#else
        sram_udelay(10000);
+#endif
 }
 static struct wm831x_pdata wm831x_platdata = {
 

diff --git a/arch/arm/mach-rk30/pm.c b/arch/arm/mach-rk30/pm.c
index 51774b890546055c85495ee0eba6bc3950061c7e..5e081fddcce330a30e7f1e6b3d14a9e7591b99ce 100755 (executable)
--- a/arch/arm/mach-rk30/pm.c
+++ b/arch/arm/mach-rk30/pm.c
@@ -317,12 +317,13 @@ static void __sramfunc rk30_sram_suspend(void)
 {
        u32 cru_clksel0_con;
        u32 clkgt_regs[CRU_CLKGATES_CON_CNT];
+       u32 cru_mode_con;
        int i;
 
        sram_printch('5');
        ddr_suspend();
        sram_printch('6');
-
+       
        for (i = 0; i < CRU_CLKGATES_CON_CNT; i++) {
                clkgt_regs[i] = cru_readl(CRU_CLKGATES_CON(i));
        }
@@ -351,18 +352,30 @@ static void __sramfunc rk30_sram_suspend(void)
                          | (1 << CLK_GATE_ACLK_INTMEM3 % 16)
                          , clkgt_regs[9], CRU_CLKGATES_CON(9), 0x07ff);
 
+#ifdef CONFIG_CLK_SWITCH_TO_32K
+       cru_mode_con = cru_readl(CRU_MODE_CON);
+       cru_writel(0|
+               PLL_MODE_DEEP(APLL_ID)|
+               PLL_MODE_DEEP(DPLL_ID)|
+               PLL_MODE_DEEP(CPLL_ID)|PLL_MODE_DEEP(GPLL_ID),CRU_MODE_CON);
+       board_pmu_suspend();
+#else
        board_pmu_suspend();
-
        cru_clksel0_con = cru_readl(CRU_CLKSELS_CON(0));
        cru_writel((0x1f << 16) | 0x1f, CRU_CLKSELS_CON(0));
+#endif
 
        dsb();
        wfi();
 
+#ifdef CONFIG_CLK_SWITCH_TO_32K
+       board_pmu_resume();
+       cru_writel((0xffff<<16) | cru_mode_con, CRU_MODE_CON);
+#else
        cru_writel((0x1f << 16) | cru_clksel0_con, CRU_CLKSELS_CON(0));
-
        board_pmu_resume();
-
+#endif
+       
        for (i = 0; i < CRU_CLKGATES_CON_CNT; i++) {
                cru_writel(clkgt_regs[i] | 0xffff0000, CRU_CLKGATES_CON(i));
        }