clk: rockchip: rk3399: Modify dummy clock for VOP dclks

Because frac div need to more than 20 multiple between the numerator
and denominator, but we need to be fit many HDMI/DP freqs and may
bring serious jitter when the dclk_vopx below the dclk_vopx_frac.

Therefore, we can select dclk_vopx below the dclk_vopx_div directly.

Change-Id: If3d9051211f0b160a507f0942667796f043f4ec2
Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>

diff --git a/drivers/clk/rockchip/clk-rk3399.c b/drivers/clk/rockchip/clk-rk3399.c
index 3e81113abf3283a6d7db4154463ac62e1931a7ed..eddf6ec23005985d56a711de9a592a880be4ca26 100644 (file)
--- a/drivers/clk/rockchip/clk-rk3399.c
+++ b/drivers/clk/rockchip/clk-rk3399.c
@@ -147,8 +147,8 @@ PNAME(mux_pll_src_vpll_cpll_gpll_p)         = { "vpll", "cpll", "gpll" };
 PNAME(mux_pll_src_dmyvpll_cpll_gpll_npll_p)    = { "dummy_vpll", "cpll", "gpll", "npll" };
 PNAME(mux_pll_src_dmyvpll_cpll_gpll_24m_p)     = { "dummy_vpll", "cpll", "gpll", "xin24m" };
 
-PNAME(mux_dclk_vop0_p)                         = { "dclk_vop0_div", "dclk_vop0_frac" };
-PNAME(mux_dclk_vop1_p)                         = { "dclk_vop1_div", "dclk_vop1_frac" };
+PNAME(mux_dclk_vop0_p)                         = { "dclk_vop0_div", "dummy_dclk_vop0_frac" };
+PNAME(mux_dclk_vop1_p)                         = { "dclk_vop1_div", "dummy_dclk_vop1_frac" };
 
 PNAME(mux_clk_cif_p)                           = { "clk_cifout_div", "xin24m" };