Add support for the isLoad and isStore flags, needed by the instruction scheduler

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@16555 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/lib/Target/Target.td b/lib/Target/Target.td
index 780cf60f1aeebfe9be6fdfdb522adcc0825b9760..7219395769e6c9e77d779f5a132629f78a811be1 100644 (file)
--- a/lib/Target/Target.td
+++ b/lib/Target/Target.td
@@ -130,6 +130,8 @@ class Instruction {
   bit isBranch     = 0;     // Is this instruction a branch instruction?
   bit isBarrier    = 0;     // Can control flow fall through this instruction?
   bit isCall       = 0;     // Is this instruction a call instruction?
+  bit isLoad       = 0;     // Is this instruction a load instruction?
+  bit isStore      = 0;     // Is this instruction a store instruction?
   bit isTwoAddress = 0;     // Is this a two address instruction?
   bit isTerminator = 0;     // Is this part of the terminator for a basic block?
   bit hasDelaySlot = 0;     // Does this instruction have an delay slot?