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ARM64: dtsi: add nandc config for RK3366
author
Zhaoyifeng
<zyf@rock-chips.com>
Thu, 28 Jan 2016 07:40:55 +0000
(15:40 +0800)
committer
Zhaoyifeng
<zyf@rock-chips.com>
Thu, 28 Jan 2016 07:48:42 +0000
(15:48 +0800)
Change-Id: Ib15f6ed6e7ebb80775c57b6c496db712fcc8ea80
Signed-off-by: Zhaoyifeng <zyf@rock-chips.com>
arch/arm64/boot/dts/rockchip/rk3366.dtsi
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diff --git
a/arch/arm64/boot/dts/rockchip/rk3366.dtsi
b/arch/arm64/boot/dts/rockchip/rk3366.dtsi
index 92269d50c5903a980642bf333fcb2c1cd356a139..0bc6e9d43c91c3d6b506232c9d2af53f44d90ad0 100644
(file)
--- a/
arch/arm64/boot/dts/rockchip/rk3366.dtsi
+++ b/
arch/arm64/boot/dts/rockchip/rk3366.dtsi
@@
-139,6
+139,16
@@
(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
};
+ nandc0: nandc@ff0c0000 {
+ compatible = "rockchip,rk-nandc";
+ reg = <0x0 0xff0c0000 0x0 0x4000>;
+ interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
+ nandc_id = <0>;
+ clocks = <&cru SCLK_NANDC0>, <&cru HCLK_NANDC0>;
+ clock-names = "clk_nandc", "hclk_nandc";
+ status = "disabled";
+ };
+
saradc: saradc@ff100000 {
compatible = "rockchip,saradc";
reg = <0x0 0xff100000 0x0 0x100>;