Bye bye Pattern ISel, hello DAG ISel.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25700 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/lib/Target/X86/X86.h b/lib/Target/X86/X86.h
index 3f5332368c51625bfef2c5ee48b1bfba3d016d2c..c29fef2e607beb4e2b328204c6a9f9daf1740abd 100644 (file)
--- a/lib/Target/X86/X86.h
+++ b/lib/Target/X86/X86.h
@@ -25,7 +25,7 @@ class FunctionPass;
 class IntrinsicLowering;
 class MachineCodeEmitter;
 
-extern bool X86DAGIsel;
+extern bool X86PatIsel;
 
 /// createX86ISelPattern - This pass converts an LLVM function into a 
 /// machine code representation using pattern matching and a machine

diff --git a/lib/Target/X86/X86ISelLowering.cpp b/lib/Target/X86/X86ISelLowering.cpp
index 8a72f2618fb5ea20eaa05d7da89a85facf64d13d..236179f986b76e92113da72fd4bdf8179be8ec9d 100644 (file)
--- a/lib/Target/X86/X86ISelLowering.cpp
+++ b/lib/Target/X86/X86ISelLowering.cpp
@@ -95,7 +95,7 @@ X86TargetLowering::X86TargetLowering(TargetMachine &TM)
   setOperationAction(ISD::BIT_CONVERT, MVT::f32, Expand);
   setOperationAction(ISD::BIT_CONVERT, MVT::i32, Expand);
 
-  if (X86DAGIsel) {
+  if (!X86PatIsel) {
     setOperationAction(ISD::BRCOND         , MVT::Other, Custom);
   }
   setOperationAction(ISD::BRCONDTWOWAY     , MVT::Other, Expand);
@@ -118,7 +118,7 @@ X86TargetLowering::X86TargetLowering(TargetMachine &TM)
   setOperationAction(ISD::CTLZ             , MVT::i32  , Expand);
   setOperationAction(ISD::READCYCLECOUNTER , MVT::i64  , Custom);
 
-  if (!X86DAGIsel) {
+  if (X86PatIsel) {
     setOperationAction(ISD::BSWAP          , MVT::i32  , Expand);
     setOperationAction(ISD::ROTL           , MVT::i8   , Expand);
     setOperationAction(ISD::ROTR           , MVT::i8   , Expand);
@@ -141,7 +141,7 @@ X86TargetLowering::X86TargetLowering(TargetMachine &TM)
   // These should be promoted to a larger select which is supported.
   setOperationAction(ISD::SELECT           , MVT::i1   , Promote);
   setOperationAction(ISD::SELECT           , MVT::i8   , Promote);
-  if (X86DAGIsel) {
+  if (!X86PatIsel) {
     // X86 wants to expand cmov itself.
     setOperationAction(ISD::SELECT         , MVT::i16  , Custom);
     setOperationAction(ISD::SELECT         , MVT::i32  , Custom);
@@ -218,7 +218,7 @@ X86TargetLowering::X86TargetLowering(TargetMachine &TM)
     // Set up the FP register classes.
     addRegisterClass(MVT::f64, X86::RFPRegisterClass);
 
-    if (X86DAGIsel) {
+    if (!X86PatIsel) {
       setOperationAction(ISD::SINT_TO_FP, MVT::i16, Custom);
       setOperationAction(ISD::SINT_TO_FP, MVT::i32, Custom);
     }
@@ -456,7 +456,7 @@ X86TargetLowering::LowerCCCCallTo(SDOperand Chain, const Type *RetTy,
     break;
   }
 
-  if (X86DAGIsel) {
+  if (!X86PatIsel) {
     std::vector<MVT::ValueType> NodeTys;
     NodeTys.push_back(MVT::Other);   // Returns a chain
     NodeTys.push_back(MVT::Flag);    // Returns a flag for retval copy to use.
@@ -932,7 +932,7 @@ X86TargetLowering::LowerFastCCCallTo(SDOperand Chain, const Type *RetTy,
     break;
   }
 
-  if (X86DAGIsel) {
+  if (!X86PatIsel) {
     // Build a sequence of copy-to-reg nodes chained together with token chain
     // and flag operands which copy the outgoing args into registers.
     SDOperand InFlag;

diff --git a/lib/Target/X86/X86TargetMachine.cpp b/lib/Target/X86/X86TargetMachine.cpp
index 3ac55131e3d8fd939baf074e765bb23ee7354bcf..6207a274775055a1ea0e9212c85aa4c53121c9c2 100644 (file)
--- a/lib/Target/X86/X86TargetMachine.cpp
+++ b/lib/Target/X86/X86TargetMachine.cpp
@@ -26,7 +26,7 @@
 #include <iostream>
 using namespace llvm;
 
-bool llvm::X86DAGIsel = false;
+bool llvm::X86PatIsel = true;
 
 /// X86TargetMachineModule - Note that this is used on hosts that cannot link
 /// in a library unless there are references into the library.  In particular,
@@ -39,9 +39,9 @@ namespace {
   cl::opt<bool> DisableOutput("disable-x86-llc-output", cl::Hidden,
                               cl::desc("Disable the X86 asm printer, for use "
                                        "when profiling the code generator."));
-  cl::opt<bool, true> EnableX86DAGDAG("enable-x86-dag-isel", cl::Hidden,
-                      cl::desc("Enable DAG-to-DAG isel for X86"),
-                      cl::location(X86DAGIsel),
+  cl::opt<bool, true> EnableX86PatISel("enable-x86-pattern-isel", cl::Hidden,
+                      cl::desc("Enable the pattern based isel for X86"),
+                      cl::location(X86PatIsel),
                       cl::init(false));
   
   // Register the target.
@@ -106,10 +106,10 @@ bool X86TargetMachine::addPassesToEmitFile(PassManager &PM, std::ostream &Out,
   PM.add(createUnreachableBlockEliminationPass());
 
   // Install an instruction selector.
-  if (X86DAGIsel)
-    PM.add(createX86ISelDag(*this));
-  else
+  if (X86PatIsel)
     PM.add(createX86ISelPattern(*this));
+  else
+    PM.add(createX86ISelDag(*this));
 
   // Print the instruction selected machine code...
   if (PrintMachineCode)
@@ -173,10 +173,10 @@ void X86JITInfo::addPassesToJITCompile(FunctionPassManager &PM) {
   PM.add(createUnreachableBlockEliminationPass());
 
   // Install an instruction selector.
-  if (X86DAGIsel)
-    PM.add(createX86ISelDag(TM));
-  else
+  if (X86PatIsel)
     PM.add(createX86ISelPattern(TM));
+  else
+    PM.add(createX86ISelDag(TM));
 
   // FIXME: Add SSA based peephole optimizer here.