drm/rockchip: dsi: Add support for rk3366

Change-Id: I9edfea9652d8c56065590ea01480b49f1c432145
Signed-off-by: WeiYong Bi <bivvy.bi@rock-chips.com>

diff --git a/Documentation/devicetree/bindings/display/rockchip/dw_mipi_dsi_rockchip.txt b/Documentation/devicetree/bindings/display/rockchip/dw_mipi_dsi_rockchip.txt
index e26bfd4d819e176efb07c918985477b1af381c61..53bd63dec116a1484830b8a3db32d06ba78addfe 100644 (file)
--- a/Documentation/devicetree/bindings/display/rockchip/dw_mipi_dsi_rockchip.txt
+++ b/Documentation/devicetree/bindings/display/rockchip/dw_mipi_dsi_rockchip.txt
@@ -4,9 +4,11 @@ Rockchip specific extensions to the Synopsys Designware MIPI DSI
 Required properties:
 - #address-cells: Should be <1>.
 - #size-cells: Should be <0>.
-- compatible: "rockchip,rk3288-mipi-dsi", "snps,dw-mipi-dsi".
-  or "rockchip,rk3368-mipi-dsi", "snps,dw-mipi-dsi".
-  or "rockchip,rk3399-mipi-dsi", "snps,dw-mipi-dsi".
+- compatible: must be one of:
+       "rockchip,rk3288-mipi-dsi", "snps,dw-mipi-dsi".
+       "rockchip,rk3366-mipi-dsi", "snps,dw-mipi-dsi".
+       "rockchip,rk3368-mipi-dsi", "snps,dw-mipi-dsi".
+       "rockchip,rk3399-mipi-dsi", "snps,dw-mipi-dsi".
 - reg: Represent the physical address range of the controller.
 - interrupts: Represent the controller's interrupt to the CPU(s).
 - clocks, clock-names: Phandles to the controller's APB clock(pclk) as

diff --git a/drivers/gpu/drm/rockchip/dw-mipi-dsi.c b/drivers/gpu/drm/rockchip/dw-mipi-dsi.c
index 0d29890235a0c270deef109eac9f699cfa44a876..77b879b560dc34bdc130990305313cc05fcc11a0 100644 (file)
--- a/drivers/gpu/drm/rockchip/dw-mipi-dsi.c
+++ b/drivers/gpu/drm/rockchip/dw-mipi-dsi.c
@@ -35,6 +35,9 @@
 #define RK3288_DSI0_SEL_VOP_LIT                BIT(6)
 #define RK3288_DSI1_SEL_VOP_LIT                BIT(9)
 
+#define RK3366_GRF_SOC_CON0            0x0400
+#define RK3366_DSI_SEL_VOP_LIT         BIT(2)
+
 #define RK3399_GRF_SOC_CON19           0x6250
 #define RK3399_DSI0_SEL_VOP_LIT                BIT(0)
 #define RK3399_DSI1_SEL_VOP_LIT                BIT(4)
@@ -1162,6 +1165,19 @@ static struct dw_mipi_dsi_plat_data rk3288_mipi_dsi_drv_data = {
        .has_vop_sel = true,
 };
 
+static struct dw_mipi_dsi_plat_data rk3366_mipi_dsi_drv_data = {
+       .dsi0_en_bit = RK3366_DSI_SEL_VOP_LIT,
+       .grf_switch_reg = RK3366_GRF_SOC_CON0,
+       .max_data_lanes = 4,
+       .max_bit_rate_per_lane = 1000000000,
+       .has_vop_sel = true,
+};
+
+static struct dw_mipi_dsi_plat_data rk3368_mipi_dsi_drv_data = {
+       .max_data_lanes = 4,
+       .max_bit_rate_per_lane = 1000000000,
+};
+
 static struct dw_mipi_dsi_plat_data rk3399_mipi_dsi_drv_data = {
        .dsi0_en_bit = RK3399_DSI0_SEL_VOP_LIT,
        .dsi1_en_bit = RK3399_DSI1_SEL_VOP_LIT,
@@ -1173,21 +1189,19 @@ static struct dw_mipi_dsi_plat_data rk3399_mipi_dsi_drv_data = {
        .has_vop_sel = true,
 };
 
-static struct dw_mipi_dsi_plat_data rk3368_mipi_dsi_drv_data = {
-       .max_data_lanes = 4,
-       .max_bit_rate_per_lane = 1000000000,
-};
-
 static const struct of_device_id dw_mipi_dsi_dt_ids[] = {
        {
         .compatible = "rockchip,rk3288-mipi-dsi",
         .data = &rk3288_mipi_dsi_drv_data,
-       },{
-        .compatible = "rockchip,rk3399-mipi-dsi",
-        .data = &rk3399_mipi_dsi_drv_data,
+       }, {
+        .compatible = "rockchip,rk3366-mipi-dsi",
+        .data = &rk3366_mipi_dsi_drv_data,
        }, {
         .compatible = "rockchip,rk3368-mipi-dsi",
         .data = &rk3368_mipi_dsi_drv_data,
+       }, {
+        .compatible = "rockchip,rk3399-mipi-dsi",
+        .data = &rk3399_mipi_dsi_drv_data,
        },
        { /* sentinel */ }
 };